With advances in telecommunications, an increasing number of services rely on high data
rate spectrum access. These critical services include banking, telemedicine, and exchange …

This paper comprehensively reviews the evolution and latest advancement of ultra-low All-
Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical …

In energy-efficient processing platforms, such as wearable sensors and implantable medical
devices, dynamic voltage and frequency scaling allows optimizing the energy efficiency …

This paper proposes computational locking (C-lock) in all-digital phase-locked loops (PLLs)
to achieve rapid frequency and phase lock acquisition. The proposed approach employs a …

This paper presents a dual-loop ADPLL suitable for video pixel clock generation. The dual-
loop architecture where a fast subloop works as a DCO inside a main loop is chosen since it …

A pixel clock generator is widely utilized in the analog front-ends of digital TVs and also in
other video applications. A low integrated jitter is required for good display quality. However …

This brief presents a low-power small-area digitally controlled oscillator (DCO). The coarse-
fine architecture with binary-weighted delay stages is applied for the delay range and …

A variable-gain time-to-digital converter (TDC)-based multiplying delay-locked loop (MDLL)
clock multiplier featuring fast-locking and programmable N/M-ratio frequency multiplication …

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large
timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator …

Abstract An All-Digital Phase-Locked Loop (ADPLL) is an architecture that is widely
employed in the communication system due to the advancement of the Complementary …