High dynamic performance current-steering DAC design with nested-segment structure

W Mao, Y Li, CH Heng, Y Lian - IEEE Transactions on Very …, 2018 - ieeexplore.ieee.org
Dynamic performance of the current-steering digital-to-analog converter (DAC) is mainly
affected by the mismatch-induced nonlinearity. Dynamic-element-matching (DEM) method …

Demystifying and mitigating code-dependent switching distortions in current-steering DACs

L Lai, X Li, Y Fu, Y Liu, H Yang - IEEE Transactions on Circuits …, 2018 - ieeexplore.ieee.org
This paper analyzes the intermodulation between the element transition rate and the output-
dependent unit switching distortion, ie, the switching distortion of one switching unit, in …

Compensation and calibration techniques for current-steering DACs

SM McDonnell, VJ Patel, L Duncan… - IEEE Circuits and …, 2017 - ieeexplore.ieee.org
Digital-to-analog converters (DACs) are pervasive, critical components for radios and
various signal processing systems. Therefore, a myriad of research efforts, covering …

A switching sequence for unary digital-to-analog converters based on a knight's tour

MS Yenuchenko, AS Korotkov… - … on Circuits and …, 2019 - ieeexplore.ieee.org
This paper proposes a new switching sequence with the asymmetric placement of weighting
elements for a unary digital-to-analog converter (DAC). The proposed sequence is based on …

An 8.55–17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping

J Xiao, N Liang, B Chen, M Liu - IEEE Transactions on Very …, 2022 - ieeexplore.ieee.org
This article proposes a phase-locked loop (PLL) based on the direct digital synthesis
(DDS)/digital-to-analog converter (DAC) and the double-edge zero-crossing sampling …

A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

S Samanta, S Sarkar - AEU-International Journal of Electronics and …, 2023 - Elsevier
This article presents a low power high dynamic performance 10-bit Current Steering Digital-
to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based …

A 12-Bit Current-Steering DAC With Unary-Splitting-Binary Segmented Architecture and Improved Decoding Circuit Topology

X Tong, D Liu, R Wang - … on Very Large Scale Integration (VLSI …, 2022 - ieeexplore.ieee.org
This article presents a “three unary bits+ five splitting bits+ four binary bits” segmented 500-
MS/s current-steering digital-to-analog converter (DAC). The proposed splitting decoding …

A pairwise swap enabled randomized DEM addressing intersegment mismatch for current steering digital-to-analog converters

S Samanta, S Sarkar - IEEE Transactions on Very Large Scale …, 2022 - ieeexplore.ieee.org
Mismatch-based nonlinear distortion greatly influences the accuracy and spurious-free
dynamic range (SFDR) of current steering digital-to-analog converters (CS-DACs). Dynamic …

A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) in 55 nm CMOS technology

D Wang, X Guo, L Zhou, D Wu, J Luan, H Liu, J Wu… - Electronics, 2019 - mdpi.com
A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm
complementary metal–oxide–semiconductor (CMOS) technology has been presented. A …

A 65-nm CMOS 1 GS/s 45mW Hybrid Digital-to-Analog Converter (DAC) with Digital Deglitch Mechanism Achieving 13.83 fJ/step FOM for 5G New Radio Sub-6 GHz …

N Idros, J Rajendran, S Mariappan, L Yizhi… - IEEE …, 2024 - ieeexplore.ieee.org
This paper presents a high speed 16-bit hybrid Digital-to-Analog converter (DAC) featuring
an innovative digital filtering mechanism designed to eliminate glitches and ensure high …