Experimental demonstration and evaluation of BCH-coded UWOC link for power-efficient underwater sensor nodes

M Salman, J Bolboli, WY Chung - IEEE Access, 2022 - ieeexplore.ieee.org
Mobile nodes can encounter many challenges in underwater environments during
communication due to turbidity, suspended particles, small bubbles, and turbulence. These …

Design and implementation of a DVB-S2 reconfigurable datapath BCH encoder for high data-rate payload data telemetry

G Quintarelli, M Bertolucci, P Nannipieri - IEEE Access, 2023 - ieeexplore.ieee.org
To ensure the flexibility of Earth Observation satellite missions, it is essential to have highly
adaptable communication systems equipped with efficient modulation and coding schemes …

[PDF][PDF] Power spectral density analysis of speech signal using window techniques

J Saini, R Mehra - International Journal of Computer Applications, 2015 - researchgate.net
In this paper a comparative analysis of speech signal is performed using different window
techniques. As each communication system consists of three major parts that are transmitter …

A low error rate BCH-based encoder-decoder approach for electromagnetic measurement while drilling system

C Zhang, H Dong, J Wang, J Ge, H Liu, Z Yuan… - IEEE …, 2019 - ieeexplore.ieee.org
In practical applications of electromagnetic measurement while drilling (EM-MWD) in the
underground coal mine, the signal-to-noise ratio (SNR) of a receiver cannot always meet the …

[PDF][PDF] Implementation of encoder for (31, k) binary BCH code based on FPGA for multiple error correction control

SJ Mohammed - International Journal of Computer Applications, 2013 - academia.edu
This paper describes the design and implementation of (31, k) binary BCH (Bose,
Chaudhuri, and Hocquenghem) encoder using a Field Programmable Gate Array (FPGA) …

[PDF][PDF] FPGA implementation of 3 bits BCH error correcting codes

SJ Mohammed, HF Abdulsada - International Journal of Computer …, 2013 - Citeseer
This paper describes the prototyping of a BCH (Bose, Chaudhuri, and Hocquenghem) code
using a Field Programmable Gate Array (FPGA) reconfigurable chip. BCH code is one of the …

Design of any codeword length parallel long BCH encoders with the help of an efficient C-utility

S Koorapati - … on VLSI Systems, Architecture, Technology and …, 2015 - ieeexplore.ieee.org
Error correction has become crucial for NAND Flash based Solid State Drives. As we move
towards MLC (Multi Level Cell) NAND Flash memories from SLC (Single Level Cell) NAND …

Investigating Power-Temperature Dependencies in Encoder Implementations: A Comparative Perspective

G Singh, A Kaur - 2024 Asia Pacific Conference on Innovation …, 2024 - ieeexplore.ieee.org
A technique for creating energy-efficient encoders, specifically for FPGA families, is
presented in this research work. In conventional systems, energy optimization is often …

Comparative Analysis and Review of FPGA Based FEC Codes

P Rohith, M Ramesha - 2022 International Interdisciplinary …, 2022 - ieeexplore.ieee.org
Forward error correction (FEC) codes corrects the error bits in transmission channel. The
FEC codes are more suitable for applications like digital video broadcasting (DVB) satellite …

Разработка структуры быстродействующего декодера БЧХ-кода (15, 7, 5) на основе метода циклического декодирования

ЕА Мыцко, АН Мальчуков, СЕ Рыжова… - Прикладная …, 2017 - elibrary.ru
Авторами приведено общее описание метода циклического декодирования БЧХ-кода.
Представлена структура декодера БЧХ-кода (15, 7, 5), исправляющего двукратные …