A survey on compiler autotuning using machine learning

AH Ashouri, W Killian, J Cavazos, G Palermo… - ACM Computing …, 2018 - dl.acm.org
Since the mid-1990s, researchers have been trying to use machine-learning-based
approaches to solve a number of different compiler optimization problems. These …

Reconfigurable hardware accelerators: Opportunities, trends, and challenges

C Wang, W Lou, L Gong, L Jin, L Tan, Y Hu, X Li… - arXiv preprint arXiv …, 2017 - arxiv.org
With the emerging big data applications of Machine Learning, Speech Recognition, Artificial
Intelligence, and DNA Sequencing in recent years, computer architecture research …

Graph neural networks for high-level synthesis design space exploration

L Ferretti, A Cini, G Zacharopoulos, C Alippi… - ACM Transactions on …, 2022 - dl.acm.org
High-level Synthesis (HLS) Design-Space Exploration (DSE) aims at identifying Pareto-
optimal synthesis configurations whose exhaustive search is unfeasible due to the design …

Lattice-traversing design space exploration for high level synthesis

L Ferretti, G Ansaloni, L Pozzi - 2018 IEEE 36th International …, 2018 - ieeexplore.ieee.org
This paper describes a design space exploration methodology for High Level Synthesis
(HLS) frameworks. Inputs of HLS tools are a description (usually in C/C++) of the …

The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems

F Herrera, H Posadas, P Peñil, E Villar, F Ferrero… - Journal of Systems …, 2014 - Elsevier
The design of embedded systems is being challenged by their growing complexity and tight
performance requirements. This paper presents the COMPLEX UML/MARTE Design Space …

Massively parallel skyline computation for processing-in-memory architectures

V Zois, D Gupta, VJ Tsotras, WA Najjar… - Proceedings of the 27th …, 2018 - dl.acm.org
Processing-In-Memory (PIM) is an increasingly popular architecture aimed at addressing
the'memory wall'crisis by prioritizing the integration of processors within DRAM. It promotes …

Design space exploration for chiplet-assembly-based processors

S Pal, D Petrisko, R Kumar… - IEEE Transactions on Very …, 2020 - ieeexplore.ieee.org
Recent advancements in 2.5-D integration technologies have made chiplet assembly a
viable system design approach. Chiplet assembly is emerging as a new paradigm for …

The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration

K Grüttner, PA Hartmann, K Hylla, S Rosinger… - Microprocessors and …, 2013 - Elsevier
The consideration of an embedded device's power consumption and its management is
increasingly important nowadays. Currently, it is not easily possible to integrate power …

Mlgoperf: An ml guided inliner to optimize performance

AH Ashouri, M Elhoushi, Y Hua, X Wang… - arXiv preprint arXiv …, 2022 - arxiv.org
For the past 25 years, we have witnessed an extensive application of Machine Learning to
the Compiler space; the selection and the phase-ordering problem. However, limited works …

Application autotuning to support runtime adaptivity in multicore architectures

D Gadioli, G Palermo, C Silvano - … International Conference on …, 2015 - ieeexplore.ieee.org
In this work, we introduce an application autotuning framework to dynamically adapt
applications in multicore architectures. In particular, the framework exploits design-time …