The explosion of artificial intelligence and machine-learning algorithms, connected to the
exponential growth of the exchanged data, is driving a search for novel application-specific …

Selective area atomic layer deposition (SA-ALD) offers the potential to replace a lithography
step and provide a significant advantage to mitigate pattern errors and relax design rules in …

This work developed a plasma atomic layer etching (ALE) process for molybdenum (Mo)
with surface fluorination and ion bombardment. The Mo surface was fluorinated with CHF 3 …

With the rapid development of semiconductors, the number of materials needed to be
polished sharply increases. The material properties vary significantly, posing challenges to …

Non-volatile (NV) nano-electro-mechanical (NEM) switches are successfully implemented
using multiple metallic layers in a standard 65 nm CMOS back-end-of-line (BEOL) process …

In this paper, we study the main interconnect aging processes: electromigration,
thermomigration and stress migration and propose comprehensive yet compact models for …

Copper interconnects have gained wide acceptance in the microelectronics industry due to
improved resistivity and reliability compared to Al interconnects. Initially SiO 2 was used as …

An on-wafer micro-detector for in situ EUV (wavelength of 13.5 nm) detection featuring
FinFET CMOS compatibility, 1 T pixel and battery-less sensing is demonstrated. Moreover …

Electrical test measurement in the back-end of line (BEOL) is crucial for wafer and die
sorting as well as comparing intended process splits. Any in-line, nondestructive technique …

For better gap fill in beyond 56nm pitch Cu interconnect structures, Ru liner is one of the
most promising solutions with better coverage and wettability. In this paper several new …