Apparatus, system, and method for conditional and atomic storage operations

D Flynn, D Nellans, X Ouyang - US Patent 8,601,222, 2013 - Google Patents
An apparatus, system, and method are disclosed for implementing conditional storage
operations. Storage clients access and allocate portions of an address space of a non …

Apparatus, system, and method for atomic storage operations

D Flynn, S Uphoff, X Ouyang, D Nellans… - US Patent …, 2018 - Google Patents
A storage layer (SL) for a non-volatile storage device presents a logical address space of a
non-volatile storage device to storage clients. Storage metadata assigns logical identifiers in …

Systems, methods, and interfaces for vector input/output operations

A Batwara, JG Peterson, N Talagala, N Piggin… - US Patent …, 2016 - Google Patents
Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-
contiguous logical identifier ranges are stored contiguously within a log on a non-volatile …

Systems, methods, and interfaces for managing persistent data of atomic storage operations

JG Peterson, A Batwara, N Talagala… - US Patent 10,133,662, 2018 - Google Patents
A storage controller is configured to implement an atomic storage operation comprising a
plurality of separate storage operations on a non-volatile storage medium. The storage …

Evict on write, a management strategy for a prefetch unit and/or first level cache in a multiprocessor system with speculative execution

A Gara, M Ohmacht - US Patent 8,838,906, 2014 - Google Patents
In a multiprocessor System with at least two levels of cache, a speculative thread may run on
a core processor in parallel with other threads. When the thread seeks to do a write to main …

Enhanced integrity through atomic writes in cache

D Flynn, N Talagala - US Patent 9,910,777, 2018 - Google Patents
A system and method facilitate processing atomic storage requests. The method includes
receiving, from a storage client, an atomic storage request for a first storage device that is …

Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format

S Maiyuran, S Marwaha, A Garg, S Pal, J Parra… - US Patent …, 2022 - Google Patents
Described herein is a graphics processing unit (GPU) comprising a single instruction,
multiple thread (SIMT) multiprocessor comprising an instruction cache, a shared memory …

Apparatus, system, and method for conditional and atomic storage operations

D Flynn, D Nellans, X Ouyang - US Patent 9,983,993, 2018 - Google Patents
An apparatus, system, and method are disclosed for implementing conditional storage
operations. Storage clients access and allocate portions of an address space of a non …

Apparatus, systems, and methods for nameless writes

D Flynn, D Nellans, X Ouyang - US Patent 9,015,425, 2015 - Google Patents
An apparatus, System, and method are disclosed for imple menting nameless storage
operations. Storage clients can access and allocate portions of an address space of a non …

Systems and methods for improving cache efficiency and utilization

A Koker, J Ray, B Ashbaugh, J Pearce, A Appu… - US Patent …, 2023 - Google Patents
US11620256B2 - Systems and methods for improving cache efficiency and utilization - Google
Patents US11620256B2 - Systems and methods for improving cache efficiency and utilization …