A tutorial on geometric programming

S Boyd, SJ Kim, L Vandenberghe, A Hassibi - Optimization and …, 2007 - Springer
A geometric program (GP) is a type of mathematical optimization problem characterized by
objective and constraint functions that have a special form. Recently developed solution …

An industrial view of electronic design automation

D MacMillen, R Camposano, D Hill… - IEEE transactions on …, 2000 - ieeexplore.ieee.org
The automation of the design of electronic systems and circuits [electronic design
automation (EDA)] has a history of strong innovation. The EDA business has profoundly …

[图书][B] Dynamic power management: design techniques and CAD tools

L Benini, G DeMicheli - 2012 - books.google.com
Dynamic power management is a design methodology aiming at controlling performance
and power levels of digital circuits and systems, with the goal of extending the autonomous …

[图书][B] Statistical analysis and optimization for VLSI: Timing and power

A Srivastava, D Sylvester, D Blaauw - 2006 - books.google.com
Statistical Analysis and Optimization For VLSI: Timing and Power is a state-of-the-art book
on the newly emerging field of statistical computer-aided design (CAD) tools. The very latest …

Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks

D Bhattacharya, V Boppana, R Roy, J Roy - US Patent 7,225,423, 2007 - Google Patents
A system and method for designing ICs, including the steps of: analyzing and optimizing a
target IC design based on design-specific objectives; partitioning the optimized target IC …

Gate sizing for constrained delay/power/area optimization

O Coudert - IEEE Transactions on Very Large Scale Integration …, 1997 - ieeexplore.ieee.org
Gate sizing has a significant impact on the delay, power dissipation, and area of the final
circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the …

Statistical gate sizing for timing yield optimization

D Sinha, NV Shenoy, H Zhou - ICCAD-2005. IEEE/ACM …, 2005 - ieeexplore.ieee.org
Variability in the chip design process has been relatively increasing with technology scaling
to smaller dimensions. Using worst case analysis for circuit optimization severely over …

A new statistical optimization algorithm for gate sizing

M Mani, M Orshansky - IEEE International Conference on …, 2004 - ieeexplore.ieee.org
In this paper, we approach the gate sizing problem in VLSI circuits in the context of
increasing variability of process and circuit parameters as technology scales into the …

Incremental cad

O Coudert, J Cong, S Malik… - IEEE/ACM International …, 2000 - ieeexplore.ieee.org
Comprehensive study of incremental algorithms and solutions in the context of CAD tool
development is an open area of research with a great deal of potential. Incremental …

An efficient method for large-scale gate sizing

S Joshi, S Boyd - IEEE Transactions on Circuits and Systems I …, 2008 - ieeexplore.ieee.org
We consider the problem of choosing the gate sizes or scale factors in a combinational logic
circuit in order to minimize the total area, subject to simple RC timing constraints, and a …