Spatial interpolated lookup tables (LUTs) models for ergodic capacity of MIMO FSO systems
We propose low complexity, adaptive multivariate precomputed B-spline and Barycentric
Lagrange interpolation-based lookup table (B 2 LUT) models for the estimation of channel …
Lagrange interpolation-based lookup table (B 2 LUT) models for the estimation of channel …
An improved large-signal equivalent circuit model for partially depleted silicon-on-insulator MOSFET
Y Wu, X Du, Q Wang, H Liu, Y Yu… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In this article, a nonlinear capacitance model for a large-signal compact model of partially
depleted (PD) silicon-on-insulator (SOI) transistors is proposed. When the transistors are …
depleted (PD) silicon-on-insulator (SOI) transistors is proposed. When the transistors are …
A novel hierarchical circuit LUT model for SOI technology for rapid prototyping
S Roymohapatra, GR Gore, A Yadav… - … on Computer-Aided …, 2019 - ieeexplore.ieee.org
In this paper, a new look-up table (LUT) method is proposed to reduce the simulation time
and the run time memory requirement for large logic and mixed signal simulations. In the …
and the run time memory requirement for large logic and mixed signal simulations. In the …