The span cache is a hardware-software design for a new kind of energy-efficient
microprocessor data cache which has two key features. The first is direct addressing which …

Optimizing for instruction caches, part 1. Kleen et al. EE Times, Oct. 29, 2007, retrieved from
http://www. eetimes. com/document. asp? doc id= 1275470 on Jan. 28, 2007 (3 pages) …

Focusing on the way-predicting cache with sub-block placement, we propose a new cache
scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary …

The trade-off between direct-mapped caches and set-associative caches is an important
issue in the research on the performance of caches. The conventional set-associative …

In one embodiment, a microprocessor is provided. The microprocessor includes instruction
memory and a branch prediction unit. The branch prediction unit is configured to use …

A way-determination scheme for an n-way associative cache is provided that is based on the
entirety of the line address of a requested data item, thereby eliminating the possibility of a …

Energy efficiency of cache memories is crucial in designing embedded processors.
Reducing energy consumption in the instruction cache is especially important, since the …

In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with
respect to the two conventional schemes namely set-associative and direct mapping. Similar …

Set-associative caches achieve low miss rates for typical applications but result in significant
energy dissipation. For low energy, we introduce a new cache design, partial tag …

The conjugacy search problem in a group G is the problem of recovering an x¿ G from given
g¿ G and h= x-1 gx. The alleged computational hardness of this problem in some groups …