Characterization and modeling of gigarad-TID-induced drain leakage current of 28-nm bulk MOSFETs

CM Zhang, F Jazaeri, G Borghello… - … on Nuclear Science, 2018 - ieeexplore.ieee.org
This paper characterizes and models the effects of total ionizing dose (TID) up to 1 Grad
(SiO 2) on the drain leakage current of nMOSFETs fabricated with a commercial 28-nm bulk …

Timespot1: a 28 nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

S Cadeddu, L Frontini, A Lai, V Liberali… - Journal of …, 2023 - iopscience.iop.org
We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm
technology, featuring a 32× 32 pixel matrix with a pitch of 35 μm. Timespot1 is the first small …

[HTML][HTML] A generalized EKV charge-based MOSFET model including oxide and interface traps

CM Zhang, F Jazaeri, G Borghello, S Mattiazzo… - Solid-State …, 2021 - Elsevier
This paper presents a generalized EKV charge-based MOSFET model that includes the
effects of trapped charges in the oxide bulk and at the silicon/oxide interface. It is shown that …

Total-ionizing dose irradiation induced degradation behavior and mechanism of the Cascode GaN HEMTs

XZ Cai, YQ Chen, CJ Zhou - Semiconductor Science and …, 2023 - iopscience.iop.org
In this article, the effects of total ionizing dose (TID) irradiation and the annealing treatment
on the degradation of the commercial Cascode GaN high-electron-mobility transistors …

Reliability of Advanced Nanoscale CMOS Technology for High-Radiation Environments

G Termo - 2024 - infoscience.epfl.ch
Ionizing and non-ionizing radiation is known to cause damages in electronic components,
resulting in reduced performance and possible failure. This is a major issue for any …

[PDF][PDF] An Analog Pixel Front-End for High Granularity Space-Time Measurements

L Piccolo - 2022 - tesidottorato.depositolegale.it
This thesis describes the results of the design and characterization work done to develop an
analog front-end for a pixel front-end Application Specific Integrated Circuit (ASIC) with time …

Precise Model of the Effective Threshold Voltage Changes in the DLS MOSFETs for Different Gate Angles Compared with Measured Data

D Barri, P Vacula, V Kotě, M Vacula… - 2022 International …, 2022 - ieeexplore.ieee.org
This paper presents an interesting phenomenon related to the effective threshold voltage
changes (δV th, eff) in the diamond layout shape MOS transistors (DLS MOSFETs). Besides …

The Effects of Total-Ionizing-Dose on Charge-Trap Transistors and Implications for Charge-Trap Memories

RM Brewer - 2021 - ir.vanderbilt.edu
Charge-trap transistors (CTTs) are commercial CMOS process transistors that employ their
high-k-metal-gate dielectric layers to store charge in the gate oxide for use as embedded …

Vylepšení elektrických vlastností MOSFET součástek v integrovaných obvodech pomocí topologie

B Dalibor - 2021 - dspace.cvut.cz
V současnosti jsou kritéria na ekologii a ochranu životního prostředí velmi přísná a je
nezbytné je dodržovat. Avšak, i navzdory zavedeným pravidlům, vlastní iniciativou můžeme …

Improvements in the Electrical Performances of MOSFET's in Integrated Circuits by Physical Mask Design

D Barri - 2021 - search.proquest.com
At present, the criteria for ecology and vital environment protection are rigorous and must be
respected. However, despite the established rules, our initiative can prevent potential life …