The ideal latency for on-chip network traversal would be the delay incurred from wire
traversal alone. Unfortunately, in a realistic modular network, the latency for a packet to …

We introduce a new clocking approach for digital systems to achieve better resilience to
process, voltage, and temperature (PVT) variations. The proposed scheme is based on …

We propose a low-overhead, one-cycle timing-error detection and correction (EDAC)
technique for flip-flop based pipelines. In order to prevent data collision during local clock …