(57) ABSTRACT Systems (400, 500, 600) and methods (300) for generating a chaotic
amplitude modulated signal absent of cycloStationary features by preserving a constant …

A specialized processing block for a programmable logic device includes circuitry for
performing multiplications and sums thereof, as well as circuitry for rounding the result. The …

(57) ABSTRACT A specialized processing block for a programmable logic device
incorporates a fundamental processing unit that per forms a sum of two multiplications …

US PATENT DOCUMENTS 3,564,223. A 2f1971 Harris et al. 4,646,326 A 2/1987 Backof, Jr.
et al. 4,703,507 A 10, 1987 Holden 5,007,087 A 4, 1991 Bernstein et al. 5,048,086 A 9, 1991 …

A specialized processing block in a programmable integrated circuit device is configurable
to perform floating-point arithmetic operations at selectable different precisions. The …

US PATENT DOCUMENTS 3,564,223. A 2f1971 Harris et al. 4,646,326 A 2/1987 Backof, Jr.
et al. 4,703,507 A 10, 1987 Holden 5,007,087 A 4, 1991 Bernstein et al. 5,048,086 A 9, 1991 …

3,564,223. A 2, 1971 Harris et al. from Galois field GFIp'to Galois extension field GFIp''). 3. A
g Sir Jr. etal The encryptor is configured to generate an encrypted data 4703.507 A 10/1987 …

A plurality of specialized processing blocks in a programmable logic device, including
multipliers and circuitry for adding results of those multipliers, can be configured as a larger …

(56) References Cited 5,636,150 A 6/1997 Okamoto 5,636,368 A 6/1997 Harrison et al. US
PATENT DOCUMENTS 5,640,578 A 6/1997 Balmer et al. 5,644,519 A 7, 1997 Yatim et al …

Preuss et a1. Sutton et a1. LaBarre et a1. Koopman, Jr. samples from the received signal;
selecting a? rst set of samples from the lGSSS; and concurrently comparing each of the N …