A review of near-memory computing architectures: Opportunities and challenges
The conventional approach of moving stored data to the CPU for computation has become a
major performance bottleneck for emerging scale-out data-intensive applications due to their …
major performance bottleneck for emerging scale-out data-intensive applications due to their …
Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology
X Zou, S Xu, X Chen, L Yan, Y Han - Science China Information Sciences, 2021 - Springer
The “memory wall” problem or so-called von Neumann bottleneck limits the efficiency of
conventional computer architectures, which move data from memory to CPU for …
conventional computer architectures, which move data from memory to CPU for …
DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
Near-memory computing: Past, present, and future
The conventional approach of moving data to the CPU for computation has become a
significant performance bottleneck for emerging scale-out data-intensive applications due to …
significant performance bottleneck for emerging scale-out data-intensive applications due to …
Napel: Near-memory computing application performance prediction via ensemble learning
The cost of moving data between the memory/storage units and the compute units is a major
contributor to the execution time and energy consumption of modern workloads in …
contributor to the execution time and energy consumption of modern workloads in …
Neurostream: Scalable and energy efficient deep learning with smart memory cubes
High-performance computing systems are moving towards 2.5 D and 3D memory
hierarchies, based on High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC) to …
hierarchies, based on High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC) to …
Concurrent data structures for near-memory computing
The performance gap between memory and CPU has grown exponentially. To bridge this
gap, hardware architects have proposed near-memory computing (also called processing-in …
gap, hardware architects have proposed near-memory computing (also called processing-in …
A scalable near-memory architecture for training deep neural networks on large in-memory datasets
Most investigations into near-memory hardware accelerators for deep neural networks have
primarily focused on inference, while the potential of accelerating training has received …
primarily focused on inference, while the potential of accelerating training has received …
Cairo: A compiler-assisted technique for enabling instruction-level offloading of processing-in-memory
Three-dimensional (3D)-stacking technology and the memory-wall problem have
popularized processing-in-memory (PIM) concepts again, which offers the benefits of …
popularized processing-in-memory (PIM) concepts again, which offers the benefits of …
PIMSim: A flexible and detailed processing-in-memory simulator
With the advent of big data applications and new process technologies, Process-in-Memory
(PIM) attracts much attention in memory research as the architecture studies gradually shift …
(PIM) attracts much attention in memory research as the architecture studies gradually shift …