Interconnects for DNA, quantum, in-memory, and optical computing: insights from a panel discussion
The computing world is witnessing a proverbial Cambrian explosion of emerging paradigms
propelled by applications, such as artificial intelligence, big data, and cybersecurity. The …
propelled by applications, such as artificial intelligence, big data, and cybersecurity. The …
Improving the reliability and energy-efficiency of high-bandwidth photonic NoC architectures with multilevel signaling
Photonic network-on-chip (PNoC) architectures employ photonic waveguides with dense-
wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators …
wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators …
Exploiting process variations to secure photonic NoC architectures from snooping attacks
The compact size and high wavelength-selectivity of microring resonators (MRs) enable
photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing …
photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing …
A comparative analysis of front-end and back-end compatible silicon photonic on-chip interconnects
Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can
provide independence from the complex CMOS front-end compatible silicon photonic …
provide independence from the complex CMOS front-end compatible silicon photonic …
DyPhase: A dynamic phase change memory architecture with symmetric write latency and restorable endurance
IG Thakkar, S Pasricha - IEEE Transactions on Computer-Aided …, 2017 - ieeexplore.ieee.org
A major challenge for the widespread adoption of phase change memory (PCM) as main
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …
Securing photonic NoC architectures from hardware trojans
S Pasricha, SVR Chittamuru… - 2018 Twelfth IEEE …, 2018 - ieeexplore.ieee.org
The compact size and high wavelength selectivity of microring resonators (MRs) enable
photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing …
photonic networks-on-chip (PNoCs) to utilize dense-wavelength-division-multiplexing …
Photonic networks-on-chip employing multilevel signaling: A cross-layer comparative study
VSP Karempudi, F Sunny, IG Thakkar… - ACM Journal on …, 2022 - dl.acm.org
Photonic network-on-chip (PNoC) architectures employ photonic links with dense
wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers …
wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers …
Atria: A bit-parallel stochastic arithmetic based accelerator for in-dram cnn processing
SM Shivanandamurthy, IG Thakkar… - 2021 IEEE Computer …, 2021 - ieeexplore.ieee.org
With the rapidly growing use of Convolutional Neural Networks (CNNs) in real-world
applications related to machine learning and Artificial Intelligence (Al), several hardware …
applications related to machine learning and Artificial Intelligence (Al), several hardware …
DyPhase: A dynamic phase change memory architecture with symmetric write latency
IG Thakkar, S Pasricha - … Conference on VLSI Design and 2017 …, 2017 - ieeexplore.ieee.org
A major challenge for the widespread adoption of phase change memory (PCM) as main
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation …
One-step sneak-path free read scheme for resistive crossbar memory
Y Wang, L Rong, H Wang, G Wen - ACM Journal on Emerging …, 2017 - dl.acm.org
A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this
article. During read operation, it configures the crossbar array into a four-terminal resistance …
article. During read operation, it configures the crossbar array into a four-terminal resistance …