Silicon transistors are approaching their physical limit, calling for the emergence of a
technological revolution. As the acknowledged ultimate version of transistor channels, 2D …

Ever increasing demand for portable and battery-operated systems has led to aggressive
scaling. While technology scaling facilitates faster and high-performance devices, at the …

It has been demonstrated that the introduction of HfO 2/TiN gate stacks into CMOS
technologies provides the means to continue with traditional device gate length scaling …

Semiconductors, amongst one of the most important innovations of the 20 th century, have
played a pivotal role in the creation of a digitalized, modern industrial society. The global …

A novel voltage-ramp-stress (VRS) methodology is introduced for bias temperature
instability testing of metal-gate/high-k (MG/HK) CMOS devices. Results from VRS are …

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology
for a compact design of multivalued logic. Using the gate bias independent OFF-state …

This paper compares area scaling capabilities of many kinds of SRAM margin-assist
solutions for VT variability issues, which are based on various efforts by not only the cell …

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics
in state-of-the-art transistors for both high-performance and low-power applications. In this …

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in
overcoming the increased leakage current (Ioff). The invention of high-k/metal gate …

Parasitic capacitances have become a main issue for advanced technology nodes. In this
paper, we develop analytical models for parasitic capacitance components for several …