A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking
This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
overcome the limitations of conventional bang-bang phase-locked loops. A digital …
A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time …
A 20-GHz PLL with 20.9-fs random jitter
Y Zhao, M Forghani, B Razavi - IEEE Journal of Solid-State …, 2022 - ieeexplore.ieee.org
This article describes an integer-phase-locked loop (PLL) that incorporates a phase detector
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
sampling both the rising and falling edges of the reference clock. The circuit also uses a new …
An mm-wave synthesizer with robust locking reference-sampling PLL and wide-range injection-locked VCO
In this article, a two-stage millimeter (mm)-wave frequency synthesizer with low in-band
noise and robust locking reference-sampling techniques is presented. Using a two-stage …
noise and robust locking reference-sampling techniques is presented. Using a two-stage …
A low-jitter and low-spur charge-sampling PLL
This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL).
A charge-domain sub-sampling phase detector is introduced to achieve a high phase …
A charge-domain sub-sampling phase detector is introduced to achieve a high phase …
Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial
Y Hu, T Siriburanon… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this tutorial brief, we introduce a unified wideband phase-noise theory framework of
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …
A charge-sharing locking technique with a general phase noise theory of injection locking
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
A 3.78-GHz Type-I Sampling PLL With a Fully Passive KPD-Doubled Primary–Secondary S-PD Measuring 39.6-fsRMS Jitter, −260.2-dB FOM, and −70.96–dBc …
This paper reports an active-buffer-free type-I sampling phase-locked loop (S-PLL). We
innovate a fully-passive sampling phase detector with passive-gain multiplication after the …
innovate a fully-passive sampling phase detector with passive-gain multiplication after the …
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fsRMSJitter, −258.7-dB FOM, and −75.17-dBc Reference Spur
This article presents a low-jitter and low-spur type-II sampling phase-locked loop (S-PLL).
The innovative introduction of a differential parallel-series double-edge sampling phase …
The innovative introduction of a differential parallel-series double-edge sampling phase …
A 25.8-GHz integer-N CPPLL achieving 60-fs rms jitter and robust lock acquisition based on a time–amplifying phase–frequency detector
This article presents a 25.8-GHz integer-N charge pump phase-locked loop (CPPLL). With
the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is …
the proposed time–amplifying phase–frequency detector (TAPFD), the in-band noise is …