Methods and apparatus for forming dual metal interconnects

SA Parikh, R Tao, R Shaviv, JJ Lee, S Ganguli… - US Patent …, 2021 - Google Patents
Methods and apparatus for creating a dual metal interconnect on a substrate. In some
embodiments, a first liner of a first nitride material is deposited into at least one 1× feature …

Methods and apparatus for hybrid feature metallization

R Shaviv, I Emesh, X Wang - US Patent 11,024,537, 2021 - Google Patents
Methods and apparatus for forming an interconnect, including: depositing a first barrier layer
upon a top surface of a via and a top surface of a trench; filling the via with a first metal …

Integrated circuit devices including metal wires having etch stop layers on sidewalls thereof

T Bae, H Seo - US Patent 11,450,608, 2022 - Google Patents
Integrated circuit devices and methods of forming the same are provided. The integrated
circuit devices may include a first insulating layer and a plurality of metal wires on the first …

Forming dual metallization interconnect structures in single metallization level

HP Amanapu, CV Surisetty, RR Patlolla - US Patent 11,031,337, 2021 - Google Patents
Techniques are provided to fabricate metallic interconnect structures in a single
metallization level, wherein different width metallic interconnect structures are formed of …

Systems and methods for wafer bond monitoring

CY Wang, HC Hsu - US Patent 12,085,518, 2024 - Google Patents
Abstract Systems and methods are provided for monitoring wafer bonding and for detecting
or determining defects in a wafer bond formed between two semiconductor wafers. A wafer …

Interconnect structures having varied materials

G Luo, SY Yang, MH Lee, SL Shue - US Patent App. 17/875,953, 2022 - Google Patents
A semiconductor device includes a first underlying metal line and a second underlying metal
line in a first dielectric layer over a substrate. The semiconductor device includes a first metal …

Systems and methods for wafer bond monitoring

CY Wang, HC Hsu - US Patent 11,815,471, 2023 - Google Patents
Abstract Systems and methods are provided for monitoring wafer bonding and for detecting
or determining defects in a wafer bond formed between two semiconductor wafers. A wafer …

Interconnect structures

G Luo, SY Yang, MH Lee, SL Shue - US Patent 11,482,451, 2022 - Google Patents
A method includes receiving an integrated circuit (IC) layout having a plurality of metal
features in a metal layer. The method also includes classifying the plurality of metal features …

Method of forming a BEOL interconnect structure using a subtractive metal via first process

Y Mignot, Y Xu, HC Chen - US Patent 11,398,409, 2022 - Google Patents
A method of forming a BEOL interconnect structure having improved resistance-capacitance
is provided in which a via metal layer is created by a first metallization process and …

Via structures of passive semiconductor devices

X Rao, B Lin, B Li, C Feng, Y Setiawan… - US Patent …, 2023 - Google Patents
To achieve the foregoing and other aspects of the present disclosure, via structures of
passive semiconductor devices and methods of forming the same are presented. According …