Variability in device, circuit, and system parameters is one of the primary challenges in the
semiconductor industry. Parameter variations degrade processor performance, energy …

Correctly operating digital SoC domains at their target frequencies require the addition of
supply voltage () guardbands to account for supply droop events and temperature variation …

Resilient circuits based on in situ timing monitoring adaptive voltage–frequency scaling
(AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) …

Traditional digital systems employ independent loops to control supply voltage () and clock
frequency (). A clock regulation loop, for instance, a phase-locked loop (PLL), locks the …

Integrated circuits for ultra-low-power applications strive to minimize total system energy,
while satisfying performance requirements. The supply voltage (V_dd) can be set to a …

Conventional processors regulate the supply voltage (V DD) and clock frequency (F CLK) in
two separate and independent control loops. A buck converter, switched-capacitor, or low …

A proactive clock-gating system (PCGS) in a 7-nm Qualcomm® Hexagon™ digital signal
processor (DSP) improves performance or energy efficiency by reducing the magnitude of …

This paper presents a post-regulation power management integrated circuit for energy
harvesting applications. It incorporates a power budget tracking mechanism to adaptively …

Abstract System-on-Chips (SoC) are the engines of modern computing. Unfortunately, with
the plateauing of performance and energy efficiency benefits provided by each new process …

Conventional processors regulate the supply voltage (VDD) and clock frequency (FCLK) in
two separate and independent control loops. A buck converter, switched-capacitor, or low …