A survey of architectural techniques for near-threshold computing
S Mittal - ACM Journal on Emerging Technologies in Computing …, 2015 - dl.acm.org
Energy efficiency has now become the primary obstacle in scaling the performance of all
classes of computing systems. Low-voltage computing, specifically, near-threshold voltage …
classes of computing systems. Low-voltage computing, specifically, near-threshold voltage …
DPCS: Dynamic power/capacity scaling for SRAM caches in the nanoscale era
Fault-Tolerant Voltage-Scalable (FTVS) SRAM cache architectures are a promising
approach to improve energy efficiency of memories in the presence of nanoscale process …
approach to improve energy efficiency of memories in the presence of nanoscale process …
A fault-tolerant last level cache for CMPs operating at ultra-low voltage
A Ferrerón, J Alastruey-Benedé, DS Gracia… - Journal of Parallel and …, 2019 - Elsevier
Voltage scaling to values near the threshold voltage is a promising technique to hold off the
many-core power wall. However, as voltage decreases, some SRAM cells are unable to …
many-core power wall. However, as voltage decreases, some SRAM cells are unable to …
[图书][B] Opportunistic memory systems in presence of hardware variability
MW Gottscho - 2017 - search.proquest.com
The memory system presents many problems in computer architecture and system design.
An important challenge is worsening hardware variability that is caused by nanometer-scale …
An important challenge is worsening hardware variability that is caused by nanometer-scale …
[PDF][PDF] DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era
This architecture achieves lower static power for all effective cache capacities than a recent
more complex FTVS scheme. This is due to significantly lower overheads, despite the …
more complex FTVS scheme. This is due to significantly lower overheads, despite the …