This work presents a 25 MHz adaptive on/off-time-controlled three-level buck converter with
a fast reference tracking speed and high light load efficiency. The self-balancing scheme of …

This brief presents a bang-bang all-digital phase-locked loop (ADPLL) clock generator for
multiprocessor system-on-chip applications in Globalfoundries 28-nm superlow-power …

This paper presents a dynamic power management architecture for neuromorphic many-
core systems, such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) …

We present a dynamic voltage and frequency scaling technique within SoCs for per-core
power management: the architecture allows for individual, self triggered performance-level …

SpiNNaker2 - Towards Extremely Efficient Digital Neuromorphics and Multi-scale Brain
Emulation Page 1 SpiNNaker2 - Towards Extremely Efficient Digital Neuromorphics and …

A digital cell library operating in the near-threshold voltage (NTV) region is presented to
obtain both high energy efficiency and optimized performance. The proposed library …

The implementation of synaptic plasticity in neural simulation or neuromorphic hardware is
usually very resource-intensive, often requiring a compromise between efficiency and …

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured
in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy …

Over the last two decades, as microprocessors have evolved to achieve higher
computational performance, their power density also has increased at an accelerated rate …

This brief presents a built-in self-calibration (BISC) technique for minimization of the total
jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a …