Fully depleted SOI (FDSOI) technology
K Cheng, A Khakifirooz - Science China Information Sciences, 2016 - Springer
Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS
scaling to 22 nm node and beyond but also for improving the performances of legacy …
scaling to 22 nm node and beyond but also for improving the performances of legacy …
Scaling challenges for advanced CMOS devices
The economic health of the semiconductor industry requires substantial scaling of chip
power, performance, and area with every new technology node that is ramped into …
power, performance, and area with every new technology node that is ramped into …
Strain scaling for CMOS
This article describes various techniques for applying strain to current and future
complementary metal–oxide–semiconductor (CMOS) channels to boost CMOS …
complementary metal–oxide–semiconductor (CMOS) channels to boost CMOS …
Review of advanced CMOS technology for post-Moore era
M Li - Science China Physics, Mechanics and Astronomy, 2012 - Springer
The continuous downsizing of device has sustained Moore's law in the past 40 years. As the
power dissipation becomes more and more serious, a lot of emerging technologies have …
power dissipation becomes more and more serious, a lot of emerging technologies have …
A comparison of the SEU response of planar and FinFET D flip-flops at advanced technology nodes
Heavy-ion experimental results were used to characterize single-event upset trends in 16
nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data …
nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data …
Experimental demonstration of ultrashort-channel (3 nm) junctionless FETs utilizing atomically sharp V-grooves on SOI
S Migita, Y Morita, T Matsukawa… - IEEE Transactions …, 2014 - ieeexplore.ieee.org
Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator
substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching …
substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching …
Study of high-k/metal-gate work-function variation using Rayleigh distribution
By using a Monte Carlo simulation for the stochastic distribution of grain sizes, the work-
function variation (WFV) in high-k/metal-gate (HK/MG) is quantitatively and simply estimated …
function variation (WFV) in high-k/metal-gate (HK/MG) is quantitatively and simply estimated …
Impact of transistor architecture (bulk planar, trigate on bulk, ultrathin-body planar SOI) and material (silicon or III–V semiconductor) on variation for logic and SRAM …
N Agrawal, Y Kimura, R Arghavani… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
The need to enhance transistor performance below 22-nm node has brought in a change in
transistor architecture from planar bulk to either ultrathin-body SOI (UTB SOI) or 3-D trigate …
transistor architecture from planar bulk to either ultrathin-body SOI (UTB SOI) or 3-D trigate …
Planar fully-depleted-silicon-on-insulator technologies: Toward the 28 nm node and beyond
This paper presents a comprehensive overview of the research done in the last decade on
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …
[PDF][PDF] Gate all around FET: An alternative of FinFET for future technology nodes
Scaling of devices is reaching a brick wall because of short channel effects and quantum
behavior of carriers at this scaled level. At this level, the quantum mechanics became more …
behavior of carriers at this scaled level. At this level, the quantum mechanics became more …