It has been a long time that computer architecture and systems are optimized for efficient
execution of machine learning (ML) models. Now, it is time to reconsider the relationship …

Past research has proposed numerous hardware prefetching techniques, most of which rely
on exploiting one specific type of program context information (eg, program counter …

Machine learning has enabled significant benefits in diverse fields, but, with a few
exceptions, has had limited impact on computer architecture. Recent work, however, has …

Recent years have seen a dramatic increase in the microarchitectural complexity of
processors. This increase in complexity presents a twofold challenge for the field of …

Long-latency load requests continue to limit the performance of modern high-performance
processors. To increase the latency tolerance of a processor, architects have primarily relied …

Hardware prefetching is one of the common off-chip DRAM latency hiding techniques.
Though hardware prefetchers are ubiquitous in the commercial machines and prefetching …

Translation Lookaside Buffers, or TLBs, play a vital role in recent microarchitectural attacks.
However, unlike CPU caches, we know very little about the exact operation of these …

Hardware prefetching is a latency-hiding technique that hides the costly off-chip DRAM
accesses. However, state-of-the-art prefetchers fail to deliver performance improvement in …

Online Reinforcement Learning (RL) has been adopted as an effective mechanism in
various decision-making problems in microarchitecture. Its high adaptability and the ability to …

Data prefetching is a technique that plays a crucial role in modern high-performance
processors by hiding long latency memory accesses. Several state-of-the-art hardware …