[HTML][HTML] A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing

S Peyer, D Rautenbach, J Vygen - Journal of Discrete Algorithms, 2009 - Elsevier
We generalize Dijkstra's algorithm for finding shortest paths in digraphs with non-negative
integral edge lengths. Instead of labeling individual vertices we label subgraphs which …

Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts

S Teig, E Jacques - US Patent 7,117,468, 2006 - Google Patents
An integrated circuit is a device that includes many electronic components (eg, transistors,
resistors; diodes etc. These components are often interconnected to form multiple circuit …

Method and apparatus for routing with independent goals on different layers

J Frankle, A Caldwell - US Patent 7,480,885, 2009 - Google Patents
US PATENT DOCUMENTS 6,349,403 B1 2/2002 Dutta et al.................... T16, 12 6,353,918
B1* 3/2002 Carothers et al............... T16/8 5,360,948 A 1 1/1994 Thornberg 6,366,279 B1 …

Gridless IC layout and method and apparatus for generating such a layout

S Teig, A Caldwell, E Jacques - US Patent 6,957,411, 2005 - Google Patents
2004-03-01 Assigned to CADENCE DESIGN SYSTEMS, INC. A DELAWARE
CORPORATION reassignment CADENCE DESIGN SYSTEMS, INC. A DELAWARE …

Method and apparatus for computing capacity of a region for non-Manhattan routing

S Teig, Z Deretsky - US Patent 7,080,342, 2006 - Google Patents
For a router that allows routing in at least one non-Manhattan direction, some embodiments
of the invention provide a method of computing a capacity for non-Manhattan routing in a …

Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs

S Teig, A Caldwell - US Patent 6,895,567, 2005 - Google Patents
The present invention introduces Several methods for laying out integrated circuit designs
that use gridleSS non Manhat tan routing to connect the integrated circuit components. In …

Method and mechanism for implementing tessellation-based routing

DDJ Chyan, SS Raj - US Patent 7,222,322, 2007 - Google Patents
Disclosed are methods and mechanisms for implementing tessellation-based processing of
an integrated circuit design. Tessellation based routing of objects on an integrated circuit …

Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit

SL Pucci, EM Nequist - US Patent 7,096,445, 2006 - Google Patents
Disclosed is an improved approach for maintaining the structures for objects in a layout. A
single type of structure is maintained that can be used to store or track a polygon of any …

Method and apparatus for routing

S Teig, J Frankle - US Patent 7,171,635, 2007 - Google Patents
US7171635B2 - Method and apparatus for routing - Google Patents US7171635B2 -
Method and apparatus for routing - Google Patents Method and apparatus for routing …

Zone tree method and mechanism

E Nequist, JS Salowe, SL Pucci - US Patent 7,100,128, 2006 - Google Patents
A method of analyzing a design of an electronic circuit uses slices. The method includes
generating one or more slices, each slice comprising a contiguous region of the design, and …