A survey of architectural approaches for managing embedded DRAM and non-volatile on-chip caches

S Mittal, JS Vetter, D Li - IEEE Transactions on Parallel and …, 2014 - ieeexplore.ieee.org
Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large
increase in the size of on-chip caches. Since SRAM has low density and consumes large …

A survey of architectural techniques for managing process variation

S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …

Security vulnerabilities of emerging nonvolatile main memories and countermeasures

S Kannan, N Karimi, O Sinanoglu… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Emerging nonvolatile memory devices such as phase change memories and memristors are
replacing SRAM and DRAM. However, nonvolatile main memories (NVMM) are susceptible …

Mitigating process variability for non-volatile cache resilience and yield

S Salehi, N Khoshavi… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
While inclusion of emerging technology-based Non-Volatile Memory (NVM) devices in on-
chip memory subsystems offers excellent potential for energy savings and scalability, their …

Process variation aware data management for magnetic skyrmions racetrack memory

F Chen, Z Li, W Kang, W Zhao, H Li… - 2018 23rd Asia and …, 2018 - ieeexplore.ieee.org
Skyrmions racetrack memory (SKM) has been identified as a promising candidate for future
on-chip cache. Similar to many other nanoscale technologies, process variations also …

Investigating the effects of process variations and system workloads on reliability of STT-RAM caches

E Cheshmikhani, AMH Monazzah… - 2016 12th European …, 2016 - ieeexplore.ieee.org
In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in
on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power …

Leveraging data lifetime for energy-aware last level non-volatile sram caches using redundant store elimination

HJ Tsai, CC Chen, KH Yang, TC Yang… - Proceedings of the 51st …, 2014 - dl.acm.org
NVM has commonly been used to address increasingly large last-level caches (LLCs)
requirements by reducing leakage. However, frequent data-writing operations result in …

Visual data processing and action control using binary neural network

AV Kazantsev - … International Workshop on Image Analysis for …, 2007 - ieeexplore.ieee.org
A new model of the brain-like neural network for visual data processing and action control is
proposed. The neural network is built on discrete elements with binary input and output with …

In-Memory Computing Architecture for Deep Learning Acceleration

F Chen - 2020 - search.proquest.com
The ever-increasing demands of deep learning applications, especially the more powerful
but intensive unsupervised deep learning models, overwhelm computation capability …

High-performance and low-power magnetic material memory based cache design

Z Sun - 2014 - d-scholarship.pitt.edu
Magnetic memory technologies are very promising candidates to be universal memory due
to its good scalability, zero standby power and radiation hardness. Having a cell area much …