Built-in self-calibration circuit for monotonic digitally controlled oscillator design in 65-nm CMOS technology
CC Chung, CY Ko, SE Shen - IEEE Transactions on Circuits …, 2011 - ieeexplore.ieee.org
This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic
responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally …
responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally …
A low-cost low-power all-digital spread-spectrum clock generator
CC Chung, D Sheng, WD Ho - IEEE Transactions on Very …, 2014 - ieeexplore.ieee.org
In this brief, a low-cost low-power all-digital spread-spectrum clock generator (ADSSCG) is
presented. The proposed ADSSCG can provide an accurate programmable spreading ratio …
presented. The proposed ADSSCG can provide an accurate programmable spreading ratio …
A monotonic and low-power digitally controlled oscillator with portability for SoC applications
D Sheng, JC Lan - 2011 IEEE 54th International Midwest …, 2011 - ieeexplore.ieee.org
In this paper, a monotonic and low-power digitally controlled oscillator (DCO) with cell-
based design for System-On-Chip (SoC) applications is presented. The proposed DCO …
based design for System-On-Chip (SoC) applications is presented. The proposed DCO …
A low-power and small-area all-digital spread-spectrum clock generator in 65nm CMOS technology
CC Chung, D Sheng, WD Ho - Proceedings of Technical …, 2012 - ieeexplore.ieee.org
In this paper, a low-power and small-area all-digital spread spectrum clock generator
(ADSSCG) is presented. The proposed ADSSCG can provide a programmable spreading …
(ADSSCG) is presented. The proposed ADSSCG can provide a programmable spreading …
[PDF][PDF] An analysis of ADPLL applications in various fields
R Dinesh, R Marimuthu - Indonesian Journal of Electrical …, 2020 - pdfs.semanticscholar.org
ADPLL is now an essential component in applications like wireless sensor networks,
Internet of things, health care applications, agricultural applications, etc, and also due the …
Internet of things, health care applications, agricultural applications, etc, and also due the …
A carry chain-based ADMFC design on an FPGA for EMI reduction and noise compensation
An all-digital multi-frequency clocking (ADMFC) circuit is proposed to reduce
electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture …
electromagnetic interference (EMI) on a field-programmable gate array (FPGA) architecture …
A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications
D Sheng, CC Chung, JC Lan - 2012 4th Asia Symposium on …, 2012 - ieeexplore.ieee.org
In this paper, a monotonic and low-power digitally controlled oscillator (DCO) with cell-
based design for System-On-Chip (SoC) applications is presented. The proposed DCO …
based design for System-On-Chip (SoC) applications is presented. The proposed DCO …
A 6‐GHz spread spectrum clock generation with EMI reduction of 30.2 dB for SATA‐III applications
H Alsuraisry, JH Cheng, JA Lin, YH Kuo… - Microwave and …, 2017 - Wiley Online Library
In this letter, a 6‐GHz spread spectrum clock generation for Serial AT Attachment Generation
3 (SATA—III) applications in 0.18‐pm CMOS technology is presented. The 3rd‐order loop …
3 (SATA—III) applications in 0.18‐pm CMOS technology is presented. The 3rd‐order loop …
TP RAM 的低功耗设计及应用
周清军， 邢静 - Open Journal of Circuits and Systems, 2017 - hanspub.org
针对SoC 中TP RAM 的面积及功耗较大问题, 提出一种优化设计方法. 通过将SoC 中的TP RAM
替换成SP RAM, 并在SP RAM 外围增加读写接口转换逻辑, 使替换后的RAM 实现原TP RAM …
替换成SP RAM, 并在SP RAM 外围增加读写接口转换逻辑, 使替换后的RAM 实现原TP RAM …
SoC 中的伪双口RAM 优化设计方法及应用
周清军， 刘红侠 - 计算机辅助设计与图形学学报, 2017 - jcad.cn
针对SoC 中TP RAM 的面积及功耗较大问题, 提出一种优化设计方法. 该方法将SoC 中的TP
RAM 替换成SP RAM, 并在SP RAM 外围增加读写接口转换逻辑, 使替换后的RAM 实现原TP …
RAM 替换成SP RAM, 并在SP RAM 外围增加读写接口转换逻辑, 使替换后的RAM 实现原TP …