GARNET: A detailed on-chip network model inside a full-system simulator

N Agarwal, T Krishna, LS Peh… - 2009 IEEE international …, 2009 - ieeexplore.ieee.org
Until very recently, microprocessor designs were computation-centric. On-chip
communication was frequently ignored. This was because of fast, single-cycle on-chip …

Energy-efficient data replication in cloud computing datacenters

D Boru, D Kliazovich, F Granelli, P Bouvry… - Cluster computing, 2015 - Springer
Cloud computing is an emerging paradigm that provides computing, communication and
storage resources as a service over a network. Communication resources often become a …

Conservation cores: reducing the energy of mature computations

G Venkatesh, J Sampson, N Goulding, S Garcia… - ACM Sigplan …, 2010 - dl.acm.org
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are
currently conspiring to create a utilization wall that limits the fraction of a chip that can run at …

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

R Marculescu, UY Ogras, LS Peh… - … on computer-aided …, 2008 - ieeexplore.ieee.org
To alleviate the complex communication problems that arise as the number of on-chip
components increases, network-on-chip (NoC) architectures have been recently proposed …

Evaluation of the Raw microprocessor: An exposed-wire-delay architecture for ILP and streams

MB Taylor, W Lee, J Miller, D Wentzlaff, I Bratt… - ACM SIGARCH …, 2004 - dl.acm.org
This paper evaluates the Raw microprocessor. Raw addresses thechallenge of building a
general-purpose architecture that performswell on a larger class of stream and embedded …

Power-driven design of router microarchitectures in on-chip networks

H Wang, LS Peh, S Malik - Proceedings. 36th Annual IEEE …, 2003 - ieeexplore.ieee.org
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors,
networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric …

Thermal modeling, characterization and management of on-chip networks

L Shang, L Peh, A Kumar… - … (MICRO-37'04), 2004 - ieeexplore.ieee.org
Due to the wire delay constraints in deep submicron technology and increasing demand for
on-chip bandwidth, networks are becoming the pervasive interconnect fabric to connect …

Energy-efficient networks-on-chip architectures: Design and run-time optimization

SK Mandal, A Krishnakumar, UY Ogras - Network-on-Chip Security and …, 2021 - Springer
Abstract Networks-on-Chip (NoC) architectures have become the mainstream
communication backbone of high-end processors and systems-on-chip (SoCs) after their …

Transferring data in a parallel processing environment

A Agarwal - US Patent 7,394,288, 2008 - Google Patents
An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch
including switching circuitry to forward data over data paths from other tiles to the processor …

ISAC: Integrated space-and-time-adaptive chip-package thermal analysis

Y Yang, Z Gu, C Zhu, RP Dick… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten
reliability, performance, and economical cooling. To address these challenges, thermal …