Optical techniques for Rydberg physics in lattice geometries: A technical guide

JB Naber, J Vos, RJ Rengelink, RJ Nusselder… - The European Physical …, 2016 - Springer
We address the technical challenges when performing quantum information experiments
with ultracold Rydberg atoms in lattice geometries. We discuss the following key aspects:(i) …

Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm

CY Lau, MH Perrott - Proceedings of the 40th annual Design Automation …, 2003 - dl.acm.org
A new methodology for designing fractional-N frequency synthesizers and other phase
locked loop (PLL) circuits is presented. The approach achieves direct realization of the …

Bifurcation analysis for third-order phase-locked loops

LHA Monteiro, JRC Piqueira - IEEE Signal Processing Letters, 2004 - ieeexplore.ieee.org
Second-order phase-locked loops (PLLs) are extensively used in applications related to
recovering clock signals for synchronous demodulation in telecommunication networks. In …

General method for phase-locked loop filter analysis and design

A Carlosena, A Mànuel-Lázaro - IET circuits, devices & systems, 2008 - IET
The analysis and design of high-order phase-locked loops (PLLs) is difficult. A novel
approach is presented which allows high-order loops to be viewed as a natural extension of …

Optimal current balance control of three-level inverter under grid voltage unbalance: An adaptive dynamic programming approach

Y Yu, Z Wang, X Wan - Energies, 2019 - mdpi.com
When the grid voltage is unbalanced, the positive and negative sequence components in
the grid voltage cause grid current to be disordered. Under current balance control …

Analog IP design flow for SoC applications

M Hamour, R Saleh, S Mirabbasi… - 2003 IEEE International …, 2003 - ieeexplore.ieee.org
The analog/mixed-signal (AMS) portion of the IC design process continues to be a major
bottleneck, slowing the progress towards fully integrated system-on-chip (SoC) designs. A …

A novel design method for phase-locked loops of any order and type

A Carlosena, A Manuel-Latzaro - 2006 49th IEEE International …, 2006 - ieeexplore.ieee.org
In this paper a novel approach to the design of PLLs is presented, which can be used
regardless of their order and type. The method stems from the fact that high-frequency poles …

Analysis and design of high order digital phase locked loops

B Daniels - 2008 - eprints.maynoothuniversity.ie
The Phase Locked Loop (PLL) is an important component of many electronic devices; it can
be employed as a frequency synthesizer, for clock data recovery, and as amplitude and …

Improved structured filter design and analysis for perturbed phase-locked loops via sector and H∞ norm constraints with convex computations

SJA Bakar, NS Ahmad, P Goh - Computers & Electrical Engineering, 2020 - Elsevier
This work focuses on designing a structured filter in a phase-locked loop (PLL) system that is
perturbed by nonlinear effects from the phase comparator. The filter is designed based on …

Performance comparison and design guidelines for type II and type III PLLs

M Ugarte, A Carlosena - Circuits, Systems, and Signal Processing, 2015 - Springer
The advantages provided by Type III PLLs are poorly known, since these devices are very
often considered unstable and difficult, or even impossible, to design. In this paper, a …