Detailed design and evaluation of redundant multithreading alternatives

SS Mukherjee, M Kontz, SK Reinhardt - ACM SIGARCH Computer …, 2002 - dl.acm.org
Exponential growth in the number of on-chip transistors, coupled with reductions in voltage
levels, makes each generation of microprocessors increasingly vulnerable to transient faults …

The impact of resource partitioning on SMT processors

SE Raasch, SK Reinhardt - 2003 12th International Conference …, 2003 - ieeexplore.ieee.org
Simultaneous multithreading (SMT) increases processor throughput by multiplexing
resources among several threads. Despite the commercial availability of SMT processors …

Banked multiported register files for high-frequency superscalar microprocessors

JH Tseng, K Asanović - Proceedings of the 30th annual international …, 2003 - dl.acm.org
Multiported register files are a critical component of high-performance superscalar
microprocessors. Conventional multiported structures can consume significant power and …

CRISP: critical slice prefetching

H Litz, G Ayers, P Ranganathan - Proceedings of the 27th ACM …, 2022 - dl.acm.org
The high access latency of DRAM continues to be a performance challenge for
contemporary microprocessor systems. Prefetching is a well-established technique to …

Dynamic fine-grain leakage reduction using leakage-biased bitlines

S Heo, K Barr, M Hampton, K Asanović - ACM SIGARCH Computer …, 2002 - dl.acm.org
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast
transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic …

Efficient resource sharing in concurrent error detecting superscalar microarchitectures

JC Smolens, J Kim, JC Hoe… - … (MICRO-37'04), 2004 - ieeexplore.ieee.org
Previous proposals for soft-error tolerance have called for redundantly executing a program
as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar …

In-register duplication: Exploiting narrow-width value for improving register file reliability

J Hu, S Wang, SG Ziavras - International Conference on …, 2006 - ieeexplore.ieee.org
Protecting the register value and its data buses is crucial to reliable computing in high-
performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft …

[图书][B] Physics and technology of crystalline oxide semiconductor CAAC-IGZO: application to LSI

S Yamazaki, M Fujita - 2016 - books.google.com
This book describes the application of c-axis aligned crystalline In-Ga-Zn oxide (CAAC-
IGZO) technology in large-scale integration (LSI) circuits. The applications include Non …

Detecting malicious landing pages in malware distribution networks

G Wang, JW Stokes, C Herley… - 2013 43rd Annual IEEE …, 2013 - ieeexplore.ieee.org
Drive-by download attacks attempt to compromise a victim's computer through browser
vulnerabilities. Often they are launched from Malware Distribution Networks (MDNs) …

Register cache system not for latency reduction purpose

R Shioya, K Horio, M Goshima… - 2010 43rd Annual IEEE …, 2010 - ieeexplore.ieee.org
A register cache has been proposed to solve the problems of the huge register files of recent
super scalar processors. The register cache reduces the effective access latency of the …