Review of analog-to-digital conversion characteristics and design considerations for the creation of power-efficient hybrid data converters
SA Zahrai, M Onabajo - Journal of Low Power Electronics and …, 2018 - mdpi.com
This article reviews design challenges for low-power CMOS high-speed analog-to-digital
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …
converters (ADCs). Basic ADC converter architectures (flash ADCs, interpolating and folding …
A 6 bit 10 GS/s TI-SAR ADC with low-overhead embedded FFE/DFE equalization for wireline receiver applications
High-speed ADC front-ends in wireline receivers allow for implementing flexible, complex,
and robust equalization in the digital domain, as well as easily supporting bandwidth …
and robust equalization in the digital domain, as well as easily supporting bandwidth …
A 6-bit 2.5-GS/s time-interleaved analog-to-digital converter using resistor-array sharing digital-to-analog converter
This paper presents a 6-bit 2.5-GS/s time-interleaved (TI) successive-approximation-register
(SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog …
(SAR) analog-to-digital converter (ADC) that uses a resistor-array sharing digital-to-analog …
A 10 Gb/s hybrid ADC-based receiver with embedded analog and per-symbol dynamically enabled digital equalization
While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital
equalization for high data rate operation, the ADC and digital equalization power …
equalization for high data rate operation, the ADC and digital equalization power …
A 25 GS/s 6b TI two-stage multi-bit search ADC with soft-decision selection algorithm in 65 nm CMOS
While high-speed analog-to-digital converter (ADC) front-ends in serial link receivers enable
flexible and powerful digital signal processing-based (DSP-based) equalization, the …
flexible and powerful digital signal processing-based (DSP-based) equalization, the …
A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information
This paper presents a 7-bit 15× interleaved SAR ADC that operates up to 3 GS/s, using 180
nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage …
nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage …
A 6-bit 1.5-GS/s SAR ADC with smart speculative two-tap embedded DFE in 130-nm CMOS for wireline receiver applications
A Mahmoudi, P Torkzadeh… - IEEE Transactions on Very …, 2021 - ieeexplore.ieee.org
Implementing wireline receivers with a front-end analog-to-digital converter (ADC) allows for
complex, flexible, and robust signal processing algorithms in the digital domain, as well as …
complex, flexible, and robust signal processing algorithms in the digital domain, as well as …
Pipelined PAM-4 Direct Decision-Feedback Equalizer for Short-Reach Applications
This paper presents a new quarter-rate 4-level pulse amplitude modulation (PAM-4)
decision-feedback equalizer (DFE) architecture targeting short-reach and the onset of …
decision-feedback equalizer (DFE) architecture targeting short-reach and the onset of …
A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS
Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing
interest in backplane communications but power dissipation of the ADC and complex digital …
interest in backplane communications but power dissipation of the ADC and complex digital …
An 8-bit 2 GS/s 80 mW high accurate CMOS folding A/D converter with a symmetrical zero-crossing technique
D Kim, S Park, M Lee, S Nah, M Song - Analog Integrated Circuits and …, 2016 - Springer
Abstract An 8-bit 2 GS/s 80 mW low power and high accurate CMOS folding A/D converter
with a 45 nm CMOS process is described. In order to improve the non-linearity error of a …
with a 45 nm CMOS process is described. In order to improve the non-linearity error of a …