DMBF: Design metrics balancing framework for soft-error-tolerant digital circuits through bayesian optimization

Y Li, C Chen, X Cheng, J Han… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Radiation Hardened by Design (RHBD) is one of the main measures for solving the soft
error issue in digital circuits. However, a multi-objective optimization (MOO) problem …

Statistical modeling of soft error influence on neural networks

H Huang, X Xue, C Liu, Y Wang, T Luo… - … on Computer-Aided …, 2023 - ieeexplore.ieee.org
Soft errors in large VLSI circuits have a significant impact on computing-and memory-
intensive neural network (NN) processing. Understanding the influence of soft errors on NNs …

Layout-based soft error rate estimation framework considering multiple transient faults—From device to circuit level

HM Huang, CHP Wen - … Aided Design of Integrated Circuits and …, 2015 - ieeexplore.ieee.org
This paper investigated the soft errors caused by particle strikes, such as high-energy
neutrons, extending beyond the deep submicrometer era. Considering the structure of the …

MASkIt: Soft error rate estimation for combinational circuits

M Anglada, R Canal, JL Aragón… - 2016 IEEE 34th …, 2016 - ieeexplore.ieee.org
Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft
error rate (SER) estimation has become an important and very challenging goal. In this work …

Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations

M Raji, B Ghavami - IEEE Transactions on Very Large Scale …, 2016 - ieeexplore.ieee.org
Soft errors in combinational logic circuits are emerging as a significant reliability concern for
nanoscale VLSI designs. This paper presents a novel sensitivity-based gate sizing …

General efficient TMR for combinational circuit hardening against soft errors and improved multi-objective optimization framework

C Tan, Y Li, X Cheng, J Han… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
With the continuous scaling-down of transistors, the soft error issue of the combinational
circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are …

A layout-based soft error rate estimation and mitigation in the presence of multiple transient faults in combinational logic

C Georgakidis, GI Paliaroutis… - … on Quality Electronic …, 2020 - ieeexplore.ieee.org
Cosmic radiation resulting in transient faults to the combinational logic of Integrated Circuits
(ICs), constitutes a major reliability concern for space applications. In addition, continuous …

A placement-aware soft error rate estimation of combinational circuits for multiple transient faults in CMOS technology

GI Paliaroutis, P Tsoumanis… - … on Defect and Fault …, 2018 - ieeexplore.ieee.org
A considerable disadvantage that comes with the downscaling of the CMOS technology is
the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the …

Soft error rate estimation of combinational circuits based on vulnerability analysis

M Raji, H Pedram, B Ghavami - IET Computers & Digital …, 2015 - Wiley Online Library
Nanometer integrated circuits are getting increasingly vulnerable to soft errors and making
the soft error rate (SER) estimation an important challenge. In this study, a novel approach is …

Fast and accurate SER estimation for large combinational blocks in early stages of the design

M Anglada, R Canal, JL Aragon… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Soft Error Rate (SER) estimation is an important challenge for integrated circuits because of
the increased vulnerability brought by technology scaling. This paper presents a …