Fine-grained aging-induced delay prediction based on the monitoring of run-time stress

A Vijayan, A Koneru, S Kiamehr… - … on Computer-Aided …, 2016 - ieeexplore.ieee.org
Run-time solutions based on online monitoring and adaptation are required for resilience in
nanoscale integrated circuits, as design-time solutions and guard bands are no longer …

Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods

N Khoshavi, RA Ashraf, RF DeMara, S Kiamehr… - Integration, 2017 - Elsevier
The proposed paper addresses the overarching reliability issue of transistor aging in
nanometer-scaled circuits. Specifically, a comprehensive survey and taxonomy of …

NBTI and HCI aging prediction and reliability screening during production test

L Yu, J Ren, X Lu, X Wang - IEEE Transactions on Computer …, 2019 - ieeexplore.ieee.org
With the semiconductor manufacturing technology approaching to 14 nm and below, the
reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging …

EffiTest2: Efficient delay test and prediction for post-silicon clock skew configuration under process variations

GL Zhang, B Li, Y Shi, J Hu… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
At nanometer manufacturing technology nodes, process variations affect circuit performance
significantly. This trend leads to a large timing margin and thus overdesign in the traditional …

Fine-grained aging prediction based on the monitoring of run-time stress using DfT infrastructure

A Koneru, A Vijayan, K Chakrabarty… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
Run-time solutions based on real-time monitoring and adaptation are required for resilience
in nanoscale integrated circuits as design-time solutions and guard bands are no longer …

Implementation of aging mechanism analysis and prediction for XILINX 7-series FPGAs with a 28-nm process

Z Li, Z Huang, Q Wang, J Wang, N Luo - Sensors, 2022 - mdpi.com
Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm
process have become popular devices for computing systems. Although current generation …

Path selection and sensor insertion flow for age monitoring in FPGAs

M Ebrahimi, Z Ghaderi, E Bozorgzadeh… - … Design, Automation & …, 2016 - ieeexplore.ieee.org
This paper presents a two-step aging-aware methodology for Representative Critical Paths
(RCPs) selection from a large number of Critical Paths (CPs) in programmable logic devices …

[图书][B] Aging-induced Performance Degradation: Monitoring and Mitigation

Z Ghaderi - 2017 - search.proquest.com
One of the fundamental challenges to the performance gain in advanced semiconductor
technology is aging-induced delay degradation of transistors, which consequently increases …

Instruction-level NBTI stress estimation and its application in runtime aging prediction for embedded processors

I Moghaddasi, A Fouman, ME Salehi… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Lifetime reliability management of miniaturized CMOS devices continuously gets more
importance with the shrinking of technology size. Neither of existing design-time solutions …

BPath-RO: A Performance-and Area-Efficient In Situ Delay Measurement Scheme for Digital IC

D Li, H Liang, H Zhang, Y Wang, M Yi, Y Lu, Z Huang - Electronics, 2023 - mdpi.com
Circuit delays are increasingly sensitive to process, voltage, temperature, and aging (PVTA)
variations, severely impacting circuit performance. Accurate measurement of circuit delay is …