Direct-mapped caches are often plagued by conflict misses because they lack the
associativity to store more than one memory block in each set. However, some blocks that …

Since 1986, Hewlett-Packard has designed PA-RISC1'2 pro cessors for its technical
workstations and servers, commer cial servers, and large multiprocessor transaction …

A new processor implementing Hewlett-Packard's PA-RISC 1.1 (Precision Architecture) has
been designed. This latest design incorporates many improvements over the HP PA7100 …

As the gap between processor and memory speeds increases, cache performance becomes
more critical to overall system performance. Multi-lateral cache designs such as the Assist …

Beside traditional direct solvers iterative methods offer an efficient alternative for the solution
of systems of linear equations which arise in the solution of partial differential equations …

This multiplier array is used in the floating point coprocessor that is part of several PA-RISC
processor chips. This coprocessor is single-and double-precision IEEE compliant and is …

2.5 V, novel CMOS circuit techniques including a noise tolerant precharge (NTP) circuit and
a leakless buffer circuit are applied to a floating point macrocell for a 150MHz superscalar …

Emerging multi-issue microprocessors require effective data supply to sustain multiple
instruction processing. The data cache structure, the backbone of data supply, has been …

This dissertation analyzes a way to improve cache performance via active management of a
target cache space. As microprocessor speeds continue to grow faster than memory …

As the gap between processor and memory speeds increases, cache performance becomes
more critical to overall system performance. Behavioral cache simulation is typically used …