Performance analysis of low-power 1-bit CMOS full adder cells
AM Shams, TK Darwish… - IEEE transactions on very …, 2002 - ieeexplore.ieee.org
A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized
into smaller modules. The modules are studied and evaluated extensively. Several designs …
into smaller modules. The modules are studied and evaluated extensively. Several designs …
Reconfigurable architectures for general-purpose computing
A DeHon - 1996 - dspace.mit.edu
General-purpose computing devices allow us to (1) customize computation after fabrication
and (2) conserve area by reusing expensive active circuitry for different functions in time. We …
and (2) conserve area by reusing expensive active circuitry for different functions in time. We …
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
MH Perrott, TL Tewksbury… - IEEE journal of solid-state …, 1997 - ieeexplore.ieee.org
A digital compensation method and key circuits are presented that allow fractional-N
synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this …
synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this …
[图书][B] The VLSI handbook
WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-/spl mu/m CMOS. I. Architecture and transmitter design
A Rofougaran, G Chang, JJ Rael… - IEEE Journal of Solid …, 1998 - ieeexplore.ieee.org
A single-chip transceiver for frequency-hopped code division multiple access (CDMA) in the
900 MHz industrial, scientific and medical (ISM) band is implemented in 1-/spl mu/m CMOS …
900 MHz industrial, scientific and medical (ISM) band is implemented in 1-/spl mu/m CMOS …
An expanded benchmarking of beyond-CMOS devices based on Boolean and neuromorphic representative circuits
The latest results of benchmarking research are presented for a variety of beyond-CMOS
charge-and spin-based devices. In addition to improving the device-level models, several …
charge-and spin-based devices. In addition to improving the device-level models, several …
A micropower low-voltage multiplier with reduced spurious switching
We describe a micropower 16/spl times/16-bit multiplier (18.8/spl mu/W/MHz@ 1.1 V) for low-
voltage power-critical low speed (/spl les/5 MHz) applications including hearing aids. We …
voltage power-critical low speed (/spl les/5 MHz) applications including hearing aids. We …
[PDF][PDF] Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers
MH Perrott - 1997 - dspace.mit.edu
A digital compensation method is described that allows fractional-N frequency synthesizers
to be directly modulated at high data rates while simultaneously achieving good noise …
to be directly modulated at high data rates while simultaneously achieving good noise …
Design of a 3-V 300-MHz low-power 8-b/spl times/8-b pipelined multiplier using pulse-triggered TSPC flip-flops
JS Wang, PH Yang, D Sheng - IEEE Journal of Solid-State …, 2000 - ieeexplore.ieee.org
This paper describes the design of a low-power pipelined multiplier. It is illustrated in this
paper that the power consumption of the clocking system cannot be overlooked and the …
paper that the power consumption of the clocking system cannot be overlooked and the …
A reconfigurable multi-function computing cache architecture
A considerable portion of a chip is dedicated to a cache memory in a modern
microprocessor chip. However, some applications may not actively need all the cache …
microprocessor chip. However, some applications may not actively need all the cache …