An analog fractional-sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms
jitter, integrated from 10 kHz to 10 MHz, and a− 249.7-dB figure of merit (FoM) at the …

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …

A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth
all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC) …

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional-Nmultiplying delay-
locked loop (MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed …

We present an analog subsampling PLL based on a digital-to-time converter (DTC), which
operates with almost no performance gap (176/198 fs RMS jitter) between the integer and …

A low-jitter, low-power LC-based injection-locked clock multiplier (ILCM) with a digital
frequency-tracking loop (FTL) is presented. Based on a pulse gating technique, the …

This paper presents a 10-bit, 550-fs step Digital-to-Time Converter (DTC) used in the phase
comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a …

This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL
(SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low …

Although multiplying delay-locked loops allow clock frequency multiplication with very low
phase noise and jitter, their application has been so far limited to integer-N multiplication …