Survey of low-power testing of VLSI circuits
P Girard - IEEE Design & test of computers, 2002 - ieeexplore.ieee.org
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a
discussion of power consumption that gives reasons for and consequences of increased …
discussion of power consumption that gives reasons for and consequences of increased …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Minimized power consumption for scan-based BIST
S Gerstendörfer, HJ Wunderlich - Journal of Electronic Testing, 2000 - Springer
Power consumption of digital systems may increase significantly during testing. In this paper,
systems equipped with a scan-based built-in self-test like the STUMPS architecture are …
systems equipped with a scan-based built-in self-test like the STUMPS architecture are …
Static compaction techniques to control scan vector power dissipation
R Sankaralingam, RR Oruganti… - Proceedings 18th IEEE …, 2000 - ieeexplore.ieee.org
Excessive switching activity during scan testing can cause average power dissipation and
peak power during test to be much higher than during normal operation. This can cause …
peak power during test to be much higher than during normal operation. This can cause …
A novel word clustering algorithm based on latent semantic analysis
JR Bellegarda, JW Butzberger, YL Chow… - … , Speech, and Signal …, 1996 - ieeexplore.ieee.org
A new approach is proposed for the clustering of words in a given vocabulary. The method is
based on a paradigm first formulated in the context of information retrieval, called latent …
based on a paradigm first formulated in the context of information retrieval, called latent …
On low-capture-power test generation for scan testing
X Wen, Y Yamashita, S Kajihara… - 23rd IEEE VLSI Test …, 2005 - ieeexplore.ieee.org
Research on low-power scan testing has been focused on the shift mode, with little or no
consideration given to the capture mode power. However, high switching activity when …
consideration given to the capture mode power. However, high switching activity when …
A test vector inhibiting technique for low energy BIST design
P Girard, L Guiller, C Landrault… - … 17th IEEE VLSI Test …, 1999 - ieeexplore.ieee.org
During self-test, the switching activity of the circuit under test is significantly increased
compared to normal operation and leads to an increased power consumption which often …
compared to normal operation and leads to an increased power consumption which often …
A modified clock scheme for a low power BIST test pattern generator
P Girard, L Guiller, C Landrault… - … 19th IEEE VLSI Test …, 2001 - ieeexplore.ieee.org
In this paper, we present a new low power test-per-clock BIST test pattern generator that
provides test vectors which can reduce the switching activity during test operation. The …
provides test vectors which can reduce the switching activity during test operation. The …
A gated clock scheme for low power scan testing of logic ICs or embedded cores
Y Bonhomme, P Girard, L Guiller… - … 10th Asian Test …, 2001 - ieeexplore.ieee.org
Test power is now a big concern in large system-on-chip designs. In this paper, we present a
novel approach for minimizing power consumption during scan testing of integrated circuits …
novel approach for minimizing power consumption during scan testing of integrated circuits …
Low-capture-power test generation for scan-based at-speed testing
X Wen, Y Yamashita, S Morishima… - … Conference on Test …, 2005 - ieeexplore.ieee.org
Scan-based at-speed testing is a key technology to guarantee timing-related test quality in
the deep submicron era. However, its applicability is being severely challenged since …
the deep submicron era. However, its applicability is being severely challenged since …