Memory device including massbit counter and method of operating the same

SW Yun, LEE Han-Jun - US Patent 10,629,279, 2020 - Google Patents
(57) ABSTRACT A method of operating a memory device that includes a plurality of stages
each having a plurality of page buffers. The method including performing a verify operation …

Storage device, memory system, and read voltage decision method thereof

H Oh, S Ro, H Lee, S Kwon, O Kim, D Lee - US Patent 10,424,388, 2019 - Google Patents
A memory system includes multiple storage devices that each include a nonvolatile memory
device. A client device is configured to collect deterioration information of the nonvolatile …

Multi-deck memory device with access line and data line segregation between decks and method of operation thereof

K Sakui - US Patent 10,074,430, 2018 - Google Patents
Some embodiments include apparatuses and methods using a substrate, a first memory cell
block including first memory cell strings located over the substrate, first data lines coupled to …

Multi-deck memory device with access line and data line segregation between decks and method of operation thereof

K Sakui - US Patent 10,354,730, 2019 - Google Patents
Some embodiments include apparatuses and methods using a substrate, a first memory cell
block including first memory cell strings located over the substrate, first data lines coupled to …

Setting of reference voltage for data sensing in ferroelectric memories

CZ Zhou, KA Remack, JA Rodriguez - US Patent 9,767,879, 2017 - Google Patents
(57) ABSTRACT A method of setting the reference voltage for sensing data states in
integrated circuits including ferroelectric random access memory (FRAM) cells of the one …

3D NAND memory Z-decoder

K Sakui - US Patent 10,978,155, 2021 - Google Patents
Apparatus and methods are disclosed, including an appara tus having first and second units
of vertically arranged strings of memory cells, each unit including multiple tiers of a …

Nonvolatile semiconductor memory device with read voltage setting controller

N Tokiwa - US Patent 9,875,804, 2018 - Google Patents
A nonvolatile semiconductor memory device includes a memory cell array. The memory
cells of the memory cell array can be programmed to have different threshold voltages. A …

Multi-deck memory device including buffer circuitry under array

T Tanaka - US Patent 11,450,381, 2022 - Google Patents
Some embodiments include apparatuses and methods of using the apparatuses. One of the
apparatuses includes a substrate, a first deck including first memory cell strings located over …

Semiconductor apparatus with multiple tiers, and methods

T Tanzawa - US Patent 11,145,673, 2021 - Google Patents
Apparatus and methods are disclosed, including an apparatus that includes a number of
tiers of a first semiconductor material, each tier including at least one access line of at least …

Memory controller calculating optimal read level, memory system including the same, and operating method of memory controller

NOH Kwanwoo, S Hyeonjong, LEE Wijik… - US Patent App. 17 …, 2023 - Google Patents
2022-03-02 Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG
ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …