Hybrid communication topology and protocol for distributed-controlled cascaded H-bridge multilevel STATCOM

H Geng, S Li, C Zhang, G Yang, L Dong… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
Distributed control scheme is preferred to the multiple-modules-based system because of
the simple structure, low maintenance, and high scalability. This paper proposes a hybrid …

[PDF][PDF] International journal of advanced research in computer science and software engineering

AB Angadi, AB Angadi, KC Gull - International Journal, 2013 - academia.edu
Relational database management systems (RDMBSs) today are the predominant
technology for storing. In the past few years, the” one size fits all “-thinking concerning …

[PDF][PDF] Bluetooth embedded digital ammeter with Android app data logging

CF Soon, BH Teng, KS Tee, SL Jong… - Indonesian Journal of …, 2020 - academia.edu
Monitoring current supplies to light emitting diode (LED) luminaires is one of the reliability
tests performed manually. Bluetooth (HC-05) embedded digital ammeter was proposed to …

[PDF][PDF] Design of low power transceiver on Spartan-3 and Spartan-6 FPGA

K Kumar, B Pandey, AK Pandit… - … Journal of Innovative …, 2019 - researchgate.net
In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6
Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver …

A Novel Channel-Aware, Non-Sampling UART With Augmented Clock Frequency Resilience

TS Thomas, A Singh, S Ramanathan… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
In this brief, we present a novel Channel-Aware, Non-Sampling UART architecture. This
innovative approach, unlike conventional sampling-based techniques, utilizes timeouts and …

A Systematic Analysis of The UART Transceiver Theory and Application

H Zhang - Highlights in Science, Engineering and Technology, 2023 - drpress.org
This article introduces the theoretical foundation and application of Universal Asynchronous
Receiver/Transmitter (UART) in four chapters, including the history and structure of UART …

ASIC Implementation of UART chip having 16 Baud Rates at SCL 180 nm Technology Node

S Sharma, C Shekhar, S Qureshi - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
This paper presents the design and implementation of the UART module on the ASIC chip
using SCL 180 nm technology. The architecture of UART consists of three blocks: Signal …

Determination of UART receiver baud rate tolerance

A Singh, K Gupta, J Mala - … of the Sixth International Conference on …, 2015 - dl.acm.org
UART is one of the most widely used serial communication protocol in semiconductor
domain, and proves to be an integral part of a system irrespective of the industry being used …

Design and ASIC Implementation of Area Efficient UART Core in SCL 180nm Technology

JM Arjun, T Anujan - … Symposium on VLSI Design and Test …, 2024 - ieeexplore.ieee.org
In this paper, we present the design and implementation of an 8-bit Universal Asynchronous
Receiver-Transmitter (UART) operating at a baud rate of 9600. Our objective was to develop …

Analysis of Universal Asynchronous Receiver-Transmitter (UART)

A Gupta, C Charan - 2024 2nd International Conference on …, 2024 - ieeexplore.ieee.org
Modern communication systems depend heavily on the Universal Asynchronous Receiver
Transmitter (UART), which makes it easier for the devices to transmit data serially. An …