ESD/antenna diodes for through-silicon vias
Q Su, M Ni, ZW Tang, J Kawa, JD Sproch - US Patent 8,264,065, 2012 - Google Patents
BACKGROUND The present invention relates to methods and structures for addressing ESD
and antenna effects experienced by devices in the presence of through-silicon Vias …
and antenna effects experienced by devices in the presence of through-silicon Vias …
Through-substrate via (TSV) testing
V Bringivijayaraghavan, JM Brown - US Patent 9,157,960, 2015 - Google Patents
Various embodiments comprise apparatuses and methods for testing and repairing through-
Substrate Vias in a stack of interconnected dice. In various embodiments, an apparatus is …
Substrate Vias in a stack of interconnected dice. In various embodiments, an apparatus is …
System and method for electrical testing of through silicon vias (TSVs)
A Pagani - US Patent 9,111,895, 2015 - Google Patents
An embodiment of a testing system for carrying out electrical testing of at least one first
through via extending, at least in part, through a substrate of a first body of semiconductor …
through via extending, at least in part, through a substrate of a first body of semiconductor …
Circuits and methods for testing through-silicon vias
SK Goel - US Patent 8,436,639, 2013 - Google Patents
BACKGROUND Stacked multi-level or" 3D" integrated circuits offer sev eral advantages over
conventional 2D integrated circuits, Such as lower power consumption, faster performance …
conventional 2D integrated circuits, Such as lower power consumption, faster performance …
Method and architecture for pre-bond probing of TSVs in 3D stacked integrated circuits
K Chakrabarty, B Noia - US Patent 8,775,108, 2014 - Google Patents
On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are
provided. In accordance with certain embodiments of the invention, a die level wrapper is …
provided. In accordance with certain embodiments of the invention, a die level wrapper is …
3D-IC interposer testing structure and method of testing the structure
N Tseng, CY Yu - US Patent 8,680,882, 2014 - Google Patents
An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments
where the plurality of func tional metal wiring segments are connected in series by a plurality …
where the plurality of func tional metal wiring segments are connected in series by a plurality …
System for electrical testing of through silicon vias (TSVs)
A Pagani - US Patent 9,966,318, 2018 - Google Patents
A substrate includes first and second semiconductor layers doped with opposite conductivity
type in contact with each other at a PN junction to form a junction diode. At least one through …
type in contact with each other at a PN junction to form a junction diode. At least one through …
Integrated circuit for detecting defects of through chip via
DS Kim, JC Lee, C Kim - US Patent 8,946,869, 2015 - Google Patents
An integrated circuit that detects whether a through silicon via has defects or not, at a wafer
level. The integrated circuit includes a semiconductor substrate, a through silicon via …
level. The integrated circuit includes a semiconductor substrate, a through silicon via …
Leakage measurement structure having through silicon vias
A leakage measurement structure for through substrate vias which includes a semiconductor
substrate; a plurality of through substrate vias in the semiconductor substrate extending …
substrate; a plurality of through substrate vias in the semiconductor substrate extending …