Managing cache coherency in a data processing apparatus
US PATENT DOCUMENTS 6,272.520 B1 8/2001 Sharangpani et al. 6,338,123 B2* 1/2002
Joseph et al.................. 711/144 6,704,845 B2* 3/2004 Anderson et al.............. 711.146 …
Joseph et al.................. 711/144 6,704,845 B2* 3/2004 Anderson et al.............. 711.146 …
Bi-modal dram cache: Improving hit rate, hit latency and bandwidth
N Gulur, M Mehendale, R Manikantan… - 2014 47th Annual …, 2014 - ieeexplore.ieee.org
In this paper, we present Bi-Modal Cache-a flexible stacked DRAM cache organization
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …
Monitoring values of signals within an integrated circuit
SA Ford, A Reid - US Patent 8,185,724, 2012 - Google Patents
An integrated circuit, and method of reviewing values of one or more signals occurring within
that integrated circuit, are provided. The integrated circuit comprises processing logic for …
that integrated circuit, are provided. The integrated circuit comprises processing logic for …
Cache miss detection in a data processing apparatus
A data processing apparatus and method are provided for detecting cache misses. The data
processing apparatus has processing logic for executing a plurality of program threads, and …
processing apparatus has processing logic for executing a plurality of program threads, and …
An energy-efficient L2 cache architecture using way tag information under write-through policy
Many high-performance microprocessors employ cache write-through policy for
performance improvement and at the same time achieving good tolerance to soft errors in on …
performance improvement and at the same time achieving good tolerance to soft errors in on …
Exploiting early tag access for reducing l1 data cache energy in embedded processors
In this paper, we propose a new cache design technique, referred to as early tag access
(ETA) cache, to improve the energy efficiency of data caches in embedded processors. The …
(ETA) cache, to improve the energy efficiency of data caches in embedded processors. The …
A flexible multi-port caching scheme for reconfigurable platforms
Memory accesses contribute sunstantially to aggregate system delays. It is critical for
designers to ensure that the memory subsystem is designed efficiently, and much work has …
designers to ensure that the memory subsystem is designed efficiently, and much work has …
SRAM Operations and Simulation Methodologies at Bitcell, Subarray, and Macro Levels
HH Liu, F Catthoor - Circuit-Technology Co-Optimization of SRAM Design …, 2024 - Springer
This chapter presents a comprehensive simulation framework for evaluating margin, power,
performance, and area (PPA) in deeply scaled SRAM designs. The framework, covering …
performance, and area (PPA) in deeply scaled SRAM designs. The framework, covering …
Bi-modal dram cache: A scalable and effective die-stacked dram cache
N Gulur, M Mehendale, R Manikantan… - Proceedings of the 47th …, 2014 - dl.acm.org
In this paper, we present Bi-Modal Cache-a flexible stacked DRAM cache organization
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …
which simultaneously achieves several objectives:(i) improved cache hit ratio,(ii) moving the …
Write buffer-oriented energy reduction in the L1 data cache for embedded systems
J Lee, S Kim - IEEE Transactions on Very Large Scale …, 2015 - ieeexplore.ieee.org
In resource-constrained embedded systems, on-chip cache memories play an important role
in both performance and energy consumption. In contrast to read operations, scant regard …
in both performance and energy consumption. In contrast to read operations, scant regard …