Variation-tolerant design of D-flipflops
H Sunagawa, H Onodera - 23rd IEEE International SOC …, 2010 - ieeexplore.ieee.org
This paper discusses vulnerability of a D-flipflop (D-FF) under within-die (WID) variation. The
effect of WID variability on D-FF timing characteristics is examined and it is revealed that the …
effect of WID variability on D-FF timing characteristics is examined and it is revealed that the …
Resilience and yield of flip‐flops in future CMOS technologies under process variations and aging
C Werner, B Backs, M Wirnshofer… - IET Circuits, Devices …, 2014 - Wiley Online Library
In this study, the failure rate of flip‐flops in future 16 nm complementary metal‐oxide‐
semiconductor (CMOS) technologies is investigated. Using transistor level Monte Carlo …
semiconductor (CMOS) technologies is investigated. Using transistor level Monte Carlo …
Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology
R Suhail, P Srivastava, R Yadav… - Advances in Electrical …, 2022 - advances.vsb.cz
Leading digital circuits namely register, flipflops, state machines and counters drive
operational aspects and potential applications in Integrated Circuit (IC) industry. MOS …
operational aspects and potential applications in Integrated Circuit (IC) industry. MOS …
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation
S Nishizawa, T Ishihara… - 2014 27th IEEE …, 2014 - ieeexplore.ieee.org
This paper describes the process variation tolerant design of DFFs for low voltage operation.
Within-die random variation have a strong impact on the delay performance of DFF …
Within-die random variation have a strong impact on the delay performance of DFF …
Power Efficient Analysis of MOS Current Mode Logic Based Delay Flip Flop
R Suhail, P Srivastava, R Yadav… - Micro and Nanoelectronics …, 2022 - Springer
Prompt escalation of technology in the realm of electronics is beyond comparison.
Pronounced digital circuits like registers, buffers, counters and sequential state machines …
Pronounced digital circuits like registers, buffers, counters and sequential state machines …
Process variation aware D-Flip-Flop design using regression analysis
S Nishizawa, H Onodera - 2018 19th International Symposium …, 2018 - ieeexplore.ieee.org
This paper describes a design methodology for process variation aware D-Flip-Flop (DFF)
using regression analysis. We propose to use a regression analysis to model the worst-case …
using regression analysis. We propose to use a regression analysis to model the worst-case …
Design methodology for variation tolerant d-flip-flop using regression analysis
S Nishizawa, H Onodera - IEICE Transactions on Fundamentals of …, 2018 - search.ieice.org
This paper describes a design methodology for process variation aware D-Flip-Flop (DFF)
using regression analysis. We propose to use a regression analysis to model the worst-case …
using regression analysis. We propose to use a regression analysis to model the worst-case …
[PDF][PDF] 集積回路のエネルギー効率向上を目指した性能ばらつきの予測技術とセルライブラリの構築に関する研究
西澤真一 - 2015 - repository.kulib.kyoto-u.ac.jp
(論文内容の要旨) 本研究は, 集積回路のエネルギー効率向上を図るための重要技術として,
回路遅延の高精度な見積りを可能とするためのトランジスタ特性ばらつきと供給電圧ばらつきの …
回路遅延の高精度な見積りを可能とするためのトランジスタ特性ばらつきと供給電圧ばらつきの …