Reducing search space for fault diagnosis: A probability-based scoring approach

H Sabaghian-Bidgoli, P Behnam… - 2017 IEEE Computer …, 2017 - ieeexplore.ieee.org
Fault diagnosis is one of the most important phases in the VLSI design cycle. This paper
proposes a probabilistic solution for the fault diagnosis in the sequential scan-based circuits …

Data rate maximization by adaptive thresholding RF power management under renewable energy

W Tang, L Wang - 2010 IEEE International Conference on …, 2010 - ieeexplore.ieee.org
A new adaptive thresholding power management (ATPM) scheme is proposed to maximize
the data rate of RF circuits in distributed embedded systems powered by renewable energy …

An improved scheme for pre-computed patterns in core-based SoC architecture

E Sadredini, R Rahimi, P Foroutan… - 2016 IEEE East …, 2016 - ieeexplore.ieee.org
By advances in technology, integrated circuits have come to include more functionality and
more complexity in a single chip. Although methods of testing have improved, but the …

Validation of Hardware Security and Trust: A Survey

P Behnam - arXiv preprint arXiv:1801.00649, 2018 - arxiv.org
With ever advancing in digital system, security has been emerged as a major concern. Many
researchers all around the world come up with solutions to address various challenges that …

A novel SAT-based ATPG approach for transition delay faults

F Zokaee, H Sabaghian-Bidgoli… - … High Level Design …, 2017 - ieeexplore.ieee.org
Along with advances in modern VLSI technology, delay faults are becoming ever more
important. On the other hand, the strength of SAT-solver engines has made them an …

[PDF][PDF] Design Error Diagnosis and Correction of Digital Systems

P Behnam - researchgate.net
Verification is the procedure to check if there is a discrepancy between a design and its
specification. Debugging target is to find the location of the observed error (s). Correction …

Hybrid history-based test, utilizing a probabilistic approach to reduce test time

V Janfaza, H Sabaghian-Bidgoli… - 2017 IEEE East-West …, 2017 - ieeexplore.ieee.org
This paper presents a hybrid history-based test generation mechanism that intermittently
applies partial-test vectors to reduce test application time. Test generation is done by looking …