Electromagnetic induction attacks against embedded systems

J Selvaraj, GY Dayanıklı, NP Gaunkar, D Ware… - Proceedings of the …, 2018 - dl.acm.org
Embedded and cyber-physical systems are critically dependent on the integrity of input and
output signals for proper operation. Input signals acquired from sensors are assumed to …

A 50–64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65 nm CMOS technology

MS Chen, CKK Yang - IEEE Journal of Solid-State Circuits, 2015 - ieeexplore.ieee.org
This paper presents a complete 50-64 Gb/s serializing transmitter including a 4-tap
equalizer. An LC-based FFE structure is proposed. The FFE improves the bandwidth of the …

Design and characterization of 10 Gb/s and 1 Grad TID-tolerant optical modulator driver

G Ciarpi, S Cammarata, D Monda… - … on Circuits and …, 2022 - ieeexplore.ieee.org
This paper presents the design and the experimental characterization of a 10 Gb/s electronic
driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh …

π-Shape ESD Protection Design for Multi-Gbps High-Speed Circuits in CMOS Technology

CR Chang, ZJ Dai, CY Lin - Materials, 2023 - mdpi.com
CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD
protection circuits are needed. On-chip ESD protection is important for both component-level …

[HTML][HTML] A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications

M Eghtesadi, G Giustolisi, A Ballo, S Pennisi… - Electronics, 2024 - mdpi.com
This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s
applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo …

Compact and broadband ESD protection I/O pad using pad-stacked inductor

J Jeong, H Kim, J Park, J Shin, J Jeong - IEEE Access, 2023 - ieeexplore.ieee.org
In this paper, a compact and broadband electrostatic discharge (ESD) protection
input/output (I/O) pad for high-speed interfaces is designed and miniaturized using a pad …

Overshoot-induced failures in forward-biased diodes: A new challenge to high-speed ESD design

F Farbiz, A Appaswamy, AA Salman… - 2013 IEEE …, 2013 - ieeexplore.ieee.org
We report a new challenge to IEC protection of high-speed devices caused by current
filamentation due to voltage-overshoot effects in forward-biased diodes. While well …

A 0.4-mW/Gb/s near-ground receiver front-end with replica transconductance termination calibration for a 16-Gb/s source-series terminated transceiver

K Kaviani, A Amirkhany, C Huang, P Le… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
This paper describes a low-power receiver front-end in a bidirectional near-ground source-
series terminated (SST) interface implemented in a 40-nm CMOS process, which supports …

Robust ESD protection design for 40-Gb/s transceiver in 65-nm CMOS process

CY Lin, LW Chu, MD Ker - IEEE transactions on electron …, 2013 - ieeexplore.ieee.org
To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD
protection design has been proposed and realized in a 65-nm CMOS process. In this paper …

Low-loss I/O pad with ESD protection for K/Ka-bands applications in the nanoscale CMOS process

BW Peng, CY Lin - IEEE Transactions on Circuits and Systems …, 2018 - ieeexplore.ieee.org
The electrostatic discharge (ESD) protection devices are generally designed and employed
near the input/output (I/O) pad to avoid the impact of ESD events. The diodes operated …