Survey of low-power testing of VLSI circuits
P Girard - IEEE Design & test of computers, 2002 - ieeexplore.ieee.org
The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a
discussion of power consumption that gives reasons for and consequences of increased …
discussion of power consumption that gives reasons for and consequences of increased …
Securing designs against scan-based side-channel attacks
J Lee, M Tehranipoor, C Patel… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
Traditionally, the only standard method of testing that has consistently provided high fault
coverage has been scan test due to the high controllability and high observability this …
coverage has been scan test due to the high controllability and high observability this …
On low-capture-power test generation for scan testing
X Wen, Y Yamashita, S Kajihara… - 23rd IEEE VLSI Test …, 2005 - ieeexplore.ieee.org
Research on low-power scan testing has been focused on the shift mode, with little or no
consideration given to the capture mode power. However, high switching activity when …
consideration given to the capture mode power. However, high switching activity when …
An analysis of power reduction techniques in scan testing
J Saxena, KM Butler, L Whetsel - … International Test Conference …, 2001 - ieeexplore.ieee.org
Power consumption during scan testing is becoming a concern. Circuit switching activity
during scan shifting is high and results in high average and instantaneous power …
during scan shifting is high and results in high average and instantaneous power …
Low-power scan design using first-level supply gating
S Bhunia, H Mahmoodi, D Ghosh… - … Transactions on Very …, 2005 - ieeexplore.ieee.org
Reduction in test power is important to improve battery lifetime in portable electronic devices
employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan …
employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan …
Low-capture-power test generation for scan-based at-speed testing
X Wen, Y Yamashita, S Morishima… - … Conference on Test …, 2005 - ieeexplore.ieee.org
Scan-based at-speed testing is a key technology to guarantee timing-related test quality in
the deep submicron era. However, its applicability is being severely challenged since …
the deep submicron era. However, its applicability is being severely challenged since …
Securing scan design using lock and key technique
J Lee, M Tehranipoor, C Patel… - 20th IEEE International …, 2005 - ieeexplore.ieee.org
Scan test has been a common and useful method for testing VLSI designs due to the high
controllability and observability it provides. These same properties have recently been …
controllability and observability it provides. These same properties have recently been …
Controlling peak power during scan testing
R Sankaralingam, NA Touba - Proceedings 20th IEEE VLSI …, 2002 - ieeexplore.ieee.org
This paper presents a procedure for modifying a given set of scan vectors so that the peak
power during scan testing is kept below a specified limit without reducing fault coverage …
power during scan testing is kept below a specified limit without reducing fault coverage …
System-on-a-Chip (SoC) Solutions for IoT-Based Industrial Networks: Current Applications and Future Pathways
The rapid advancement of semiconductor technology has significantly influenced the
development and testing of System-on-a-Chip (SoC) solutions, particularly in the domain of …
development and testing of System-on-a-Chip (SoC) solutions, particularly in the domain of …
Power driven chaining of flip-flops in scan architectures
Y Bonhomme, P Girard, C Landrault… - Proceedings …, 2002 - ieeexplore.ieee.org
Power consumption during scan testing is becoming a primary concern. In this paper, we
present a novel approach for scan cell ordering which significantly reduces the power …
present a novel approach for scan cell ordering which significantly reduces the power …