A processor array containing 1000 independent processors and 12 memory modules was
fabricated in 32-nm partially depleted silicon on insulator CMOS. The programmable …

Hybrid floating-point (FP) implementations improve software FP performance without
incurring the area overhead of full hardware FP units. The proposed implementations are …

In this paper, a software floating-point emulation library for fixed-point SIMD processors is
proposed. The single instruction multiple data (SIMD) mechanism of those processors is …

The widths of data words in digital processors have a direct impact on area in application-
specific ICs (ASICs) and FPGAs. Circuit area impacts energy dissipation per workload and …

Modern semiconductor fabrication technologies now enable the construction of integrated
circuits which contain over 1000 processors on a single chip. However, for such systems to …

Sparse matrix-vector multiplication (SpMV) is a critical operation in scientific computing and
engineering applications. This thesis explores implementing SpMV kernels on a many-core …

Deep neural networks are used in many engineering applications such as autonomous
driving, image recognition, natural language processing, etc. For real time applications, low …

As transistor sizes continue to scale, more transistors are able to be used in a fixed die size.
The recent trend for general purpose processing units is to use the increased number of …

Despite floating-point (FP) being the most commonly used method for real number
representation, certain architectures are still limited to fixed-point arithmetic due to the large …

The power consumption of digital hearing aids is very restricted due to their small physical
size and the available hardware resources for signal processing are limited. However, there …