Learning-based prediction of embedded memory timing failures during initial floorplan design
Embedded memories are critical to success or failure of complex system-on-chip (SoC)
products. They can be significant yield detractors as a consequence of occupying …
products. They can be significant yield detractors as a consequence of occupying …
Variability-aware parametric yield estimation for analog/mixed-signal circuits: Concepts, algorithms, and challenges
Accurate yield estimation is always an important director of design. For analog/mixed signal
circuits, the dominant yield loss mechanisms are parametric in nature. This paper provides …
circuits, the dominant yield loss mechanisms are parametric in nature. This paper provides …
Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation
Considerable effort has been expended in the electronic design automation community in
trying to cope with the statistical timing problem. Most of this effort has been aimed at …
trying to cope with the statistical timing problem. Most of this effort has been aimed at …
Reachability-based robustness verification and optimization of SRAM dynamic stability under process variations
Y Song, H Yu, SMP DinakarRao - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
The dynamic stability margin of SRAM is largely suppressed at nanoscale due to not only
dynamic noise but also process variation. This paper introduces an analog verification for …
dynamic noise but also process variation. This paper introduces an analog verification for …
Multi-port FinFET SRAM design
Y Zhao, J Li, K Mohanram - Proceedings of the 23rd ACM international …, 2013 - dl.acm.org
Multi-port SRAMs are essential for caches and shared data structures, especially in modern
multi-core SoCs. The FinFET device, which offers high threshold voltage and high on/off …
multi-core SoCs. The FinFET device, which offers high threshold voltage and high on/off …
[图书][B] New Applications of Learning-Based Modeling in Nanoscale Integrated-Circuit Design
S Nath - 2016 - search.proquest.com
In today's leading-edge semiconductor technologies, it is increasingly difficult for IC
designers to achieve sufficient improvements of performance, power and area metrics in …
designers to achieve sufficient improvements of performance, power and area metrics in …
Statistical analysis of SRAM parametric failure under supply voltage scaling
EI Vătăjelu, J Figueras - 2010 IEEE International Conference …, 2010 - ieeexplore.ieee.org
Increased process variations in nano-scaled technologies lead to parametric failures in
embedded SRAMs. The reduction of the supply voltage in order to ensure low leakage …
embedded SRAMs. The reduction of the supply voltage in order to ensure low leakage …
A variability-aware robust design methodology for integrated circuits by geometric programming
Process variations have continuously posed significant challenges to the performance and
yield of integrated circuits (ICs). The performance modeling and robust optimization method …
yield of integrated circuits (ICs). The performance modeling and robust optimization method …
[PDF][PDF] Fast Statistical Analysis of Rare Failure Events for SRAM Circuits in High-Dimensional Variation Space
S Sun - 2015 - users.ece.cmu.edu
SRAM (static random-access memory) has been widely embedded in a large amount of
semiconductor chips. Therefore, the yield of most semiconductor chips is dominated by the …
semiconductor chips. Therefore, the yield of most semiconductor chips is dominated by the …
Variability-aware parametric yield estimation for analog/mixed-signal circuits: concepts, algorithms, and challenges
With technology scaling down to 90nm and below, process variation has become a primary
challenge for both design and fabrication of analog/mixed-signal circuits due to significantly …
challenge for both design and fabrication of analog/mixed-signal circuits due to significantly …