Given the significance of placement in IC physical design, extensive research studies
performed over the last 50 years addressed numerous aspects of global and detailed …

At modern technology nodes, improving routability and reducing total wirelength are no
longer sufficient to close timing. Incremental timing-driven placement (TDP) seeks to resolve …

In traditional physical-synthesis methodologies, the placement of flip-flops and latches is
problematic, especially for large systems on chips. A next-generation electronic-design …

As the interconnections dominate the circuit delay in nanometer technologies, placement
plays a major role to achieve timing closure since it is a main step that defines the …

Timing-driven placement is a critical step in nanometer-scale physical synthesis. To improve
design timing on a global scale, net-weight based global timing-driven placement is a …

The clock trees of high-performance synchronous circuits have many clock logic cells (eg,
clock gating cells, multiplexers and dividers) in order to achieve aggressive clock gating and …

This paper presents an incremental timing-driven placement tool, named OWARU. It
optimizes timing critical paths through a free space-aware path smoothing: the gates on …

Today, the Internet can be seen as a global marketplace populated by a huge number of
providers and consumers that exchange data from a wide range of domains. A combination …

For the last several technology generations, VLSI designs in new technology nodes have
had to confront the challenges associated with reduced scaling in wire delays. The solution …

We present an algorithm which permutes latch positions and sizes within a clock cluster to
maximize the worst slack. It preserves the clock footprint and routing, and can therefore be …