Silicon device scaling to the sub-10-nm regime
In the next decade, advances in complementary metal-oxide semiconductor fabrication will
lead to devices with gate lengths (the region in the device that switches the current flow on …
lead to devices with gate lengths (the region in the device that switches the current flow on …
Review of FinFET devices and perspective on circuit design challenges
RK Maurya, B Bhowmick - Silicon, 2022 - Springer
In recent technology, the demand for 3D multiple-gate MOSFETs such as FinFETs increase.
In this paper, FinFETs are explored and reviewed. The scaling of planar MOSFET below …
In this paper, FinFETs are explored and reviewed. The scaling of planar MOSFET below …
Inverse slope isolation and dual surface orientation integration
A semiconductor process and apparatus provide a high performance CMOS devices (108,
109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse …
109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse …
Semiconductor method and device with mixed orientation substrate
J Yan, CY Sung, DP Shum, A Gutmann - US Patent 7,298,009, 2007 - Google Patents
BACKGROUND Complementary metal oxide semiconductor (CMOS) is a dominant
technology in semiconductor device manufacture. A CMOS device includes both n-channel …
technology in semiconductor device manufacture. A CMOS device includes both n-channel …
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance
T Skotnicki, JA Hutchby, TJ King… - IEEE Circuits and …, 2005 - ieeexplore.ieee.org
The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …
Silicon CMOS devices beyond scaling
W Haensch, EJ Nowak, RH Dennard… - IBM Journal of …, 2006 - ieeexplore.ieee.org
To a large extent, scaling was not seriously challenged in the past. However, a closer look
reveals that early signs of scaling limits were seen in high-performance devices in recent …
reveals that early signs of scaling limits were seen in high-performance devices in recent …
High-performance CMOS variability in the 65-nm regime and beyond
K Bernstein, DJ Frank, AE Gattiker… - IBM journal of …, 2006 - ieeexplore.ieee.org
Recent changes in CMOS device structures and materials motivated by impending atomistic
and quantum-mechanical limitations have profoundly influenced the nature of delay and …
and quantum-mechanical limitations have profoundly influenced the nature of delay and …
Innovative materials, devices, and CMOS technologies for low-power mobile multimedia
T Skotnicki, C Fenouillet-Beranger… - IEEE transactions on …, 2007 - ieeexplore.ieee.org
The paradigm and the usage of CMOS are changing, and so are the requirements at all
levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and …
levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and …
Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing
PR Chidambaram, C Bowen… - … on Electron Devices, 2006 - ieeexplore.ieee.org
Semiconductor industry has increasingly resorted to strain as a means of realizing the
required node-to-node transistor performance improvements. Straining silicon …
required node-to-node transistor performance improvements. Straining silicon …
[图书][B] Silicon Heterostructure Handbook: Materials, Fabrication, Devices, Circuits and Applications of SiGe and Si Strained-Layer Epitaxy
JD Cressler, S Monfray, G Freeman, D Friedman… - 2018 - taylorfrancis.com
An extraordinary combination of material science, manufacturing processes, and innovative
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …
thinking spurred the development of SiGe heterojunction devices that offer a wide array of …