A 167-processor computational platform consists of an array of simple programmable
processors capable of per-processor dynamic supply voltage and clock frequency scaling …

On-chip routers typically have buffers dedicated to their input or output ports for temporarily
storing packets in case contention occurs on output physical channels. Buffers …

The design of a highly configurable continuous flow mixed-radix (CFMR) fast Fourier
transform (FFT) processor is presented. It computes fixed-point complex FFTs and inverse …

This paper presents a globally-asynchronous locally-synchronous (GALS)-compatible circuit-
switched on-chip network that is well suited for use in many-core platforms targeting …

Networks-on-Chip (NoCs) have become the de-facto on-chip interconnect for
multi/manycore systems. A typical NoC router is made up of buffers used to store packets …

We present domain adaptive processor (), a programmable systolic-array processor
designed for wireless communication and linear algebra workloads. uses a globally …

Stream processing, which involves real-time computation of data as it is created or received,
is vital for various applications, specifically wireless communication. The evolving protocols …

This paper presents a many-core heterogeneous computational platform that employs a
GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and …

Modern semiconductor fabrication technologies now enable the construction of integrated
circuits which contain over 1000 processors on a single chip. However, for such systems to …

We present a software-only implementation of an IEEE 802.11 a (WiFi) receiver optimized
for Intel multicore platforms. The receiver is about 50 times faster than a straightforward C …