We describe Btor2, a word-level model checking format for capturing models of hardware
and potentially software in a bit-precise manner. This simple, line-based and easy to parse …

We present a compositional approach to formally verify quality-of-service (QoS) properties of
network-on-chip (NoC) designs. A major challenge to scalability is the need to verify latency …

In SMT bit-vectors and thus word-level reasoning is common and widely used in industry.
However, it took until 2019 that the hardware model checking competition started to use …

This paper presents a compositional approach to formally verify quality-of-service properties
of network-on-chip designs. A major challenge to scalability is the need to verify worst-case …

In the LEC system, we employ a learning-driven approach for solving combinational data-
path equivalence checking problems. The data-path logic is specified using Boolean and …

The ever shrinking feature size of modern electronic chips leads to more designs being
done as well as more complex chips being designed. These in turn lead to greater use of …

The objective of this work is two-fold:(1) to build a simple trusted translator from C programs
to a hardware description language (in this case Verilog) and (2) to illustrate its application …

Model checking is a formal verification method that has been successfully applied to real-
world hardware and software designs. Model checking tools, however, encounter the so …

We present a satisfiability backbone-based formulation for ranking structure discovery and
thereby present an alternative scalable proof technique for the response properties. Our …

In this research, we have developed symbolic algorithms and their open-source
implementations that effectively solve liveness verification problem for industrially relevant …