Device and circuit-level performance comparison of GAA nanosheet FET with varied geometrical parameters
NA Kumari, P Prithvi - Microelectronics Journal, 2022 - Elsevier
In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations
of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For …
of the Gate all around (GAA) Nanosheet FET (NSFET) are computationally examined. For …
Gate electrode stacked source/drain SON trench MOSFET for biosensing application
This work inspects a dielectrically modulated (DM) stacked source/drain SiGe dual-metal
trench gate silicon on nothing (SON) metal–oxide–semiconductor field-effect transistor (SiGe …
trench gate silicon on nothing (SON) metal–oxide–semiconductor field-effect transistor (SiGe …
Impact of interface trap charges on device level performances of a lateral/vertical gate stacked Ge/Si TFET-on-SELBOX-substrate
This paper reports the TCAD based investigation of the DC/RF and linearity characteristics
of a newly proposed dual-material (DM) laterally-stacked (LS) SiO 2/HfO 2 heterojunction …
of a newly proposed dual-material (DM) laterally-stacked (LS) SiO 2/HfO 2 heterojunction …
Controlling ambipolarity with improved RF performance by drain/gate work function engineering and using high dielectric material in electrically doped TFET …
This article proposes a novel device structure of electrically doped tunnel FET with
drain/gate work function engineering by using hetero-dielectric material for the suppression …
drain/gate work function engineering by using hetero-dielectric material for the suppression …
Impact of ferroelectric on the electrical characteristics of silicon–germanium based heterojunction Schottky barrier FET
This work investigates the impact of ferroelectric gate oxide on high-k gate dielectric with low
band gap Silicon Germanium ferroelectric Schottky barrier FET (SiGe Fe-SBFET), has been …
band gap Silicon Germanium ferroelectric Schottky barrier FET (SiGe Fe-SBFET), has been …
[PDF][PDF] Effect of channel length variation on analog and RF performance of junctionless double gate vertical MOSFET
KE Kaharudin, F Salehuddin, ASM Zain… - J. Eng. Sci …, 2019 - researchgate.net
This paper investigates the effect of channel length (Lch) variation upon analogue and radio
frequency (RF) performance of Junctionless Double Gate Vertical MOSFET (JLDGVM). The …
frequency (RF) performance of Junctionless Double Gate Vertical MOSFET (JLDGVM). The …
High-frequency performance characteristics of the double-gate schottky barrier tunnel field effect transistor in analog and radio-frequency applications
In this paper, a novel structure of Double Gate Schottky Barrier Tunnel Field Effect Transistor
(DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) …
(DG-SBTFET) has been designed and simulated. The DG-SBTFET has two sources (NiSi) …
Variation of source gate workfunction on the performance of dual material gate rectangular recessed channel SOI‐MOSFET
This paper attempts to propose a new device as workfunction modulated dual metal
rectangular recessed channel silicon on insulator (WMDMRRC‐SOI) MOSFET. This model …
rectangular recessed channel silicon on insulator (WMDMRRC‐SOI) MOSFET. This model …
Innovative Spacer material integration in Tree-FETs for enhanced performance across Variable channel lengths
D Parvathi, P Prithvi - Micro and Nanostructures, 2024 - Elsevier
This work presents a novel three-channel Tree-FET optimized for superior DC and analog
performance metrics. The device structure features nanosheets with a width (NS WD) of 9 …
performance metrics. The device structure features nanosheets with a width (NS WD) of 9 …
Impact of structural parameters on DC performance of recessed channel SOI-MOSFET
With the concept of groove gate and implementing the idea of silicon on insulator (SOI), a
new analytical model is developed for the rectangular recessed channel silicon on insulator …
new analytical model is developed for the rectangular recessed channel silicon on insulator …